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preliminary information AMD-640 system controller data sheet tm
? 1997 advanced micro devices, inc. all rights reserved. advanced micro devices, inc. ("amd") reserves the right to make changes in its products without notice in order to improve design or performance characteristics. the information in this publication is believed to be accurate at the time of publication, but amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. amd disclaims responsibility for any consequences resulting from the use of the information included in this publication. this publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. amd products are not authorized for use as critical components in life support devices or systems without amds written approval. amd assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of amd products except as provided in amds terms and conditions of sale for such product. preliminary information trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. AMD-640, amd-645, k86, amd-k5, amd-k6, and the amd-k6 logo are trademarks of advanced micro devices, inc. mmx is a trademark of the intel corporation. microsoft and windows are registered trademarks, and windows nt is a trademark of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
3 AMD-640 system controller data sheet 21090c/0june 1997
table of contents iii 21090c/0june 1997 AMD-640 system controller data sheet preliminary information contents 1 features 1-1 1.1 processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 integrated cache controller . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.3 integrated memory controller . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.4 pci bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2overview 2-1 2.1 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 AMD-640 system controller buffers . . . . . . . . . . . . . . . . . . . 2-4 2.3 definitions, conventions, and references . . . . . . . . . . . . . . 2-5 2.3.1 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.2 related publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 3 ordering information 3-1 4 signal descriptions 4-1 4.1 processor interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 pci interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3 dram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.4 cache controller interface signals . . . . . . . . . . . . . . . . . . . 4-10 4.5 clocks and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
iv table of contents AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 5 functional operation 5-1 5.1 processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 write posting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2 read buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.3 read-around-writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2 cache controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2.1 cache organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2.2 cache operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.2.3 write buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.2.4 cacheable region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.2.5 cache parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.2.6 cache snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.3 dram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.1 mixing memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3.2 error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.3.3 dram refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.3.4 shadow ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.3.5 edo dram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.3.6 synchronous dram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.4 pci bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.4.1 pci-to-cpu (read) transactions . . . . . . . . . . . . . . . . . . . . 5-31 5.4.2 cpu-to-pci (write) transactions . . . . . . . . . . . . . . . . . . . . 5-33 5.4.3 pci arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5.4.4 pci configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5.4.5 pci transaction examples . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 5.4.6 pci accesses by another initiator . . . . . . . . . . . . . . . . . . . 5-51 5.4.7 pci fast back to back cycles . . . . . . . . . . . . . . . . . . . . . . . 5-52 5.4.8 pci sideband signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 5.4.9 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 6 initialization 6-1
table of contents v 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 7 configuration registers 7-1 7.1 pci configuration mechanism . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 pci configuration space registers . . . . . . . . . . . . . . . . . . . . 7-5 7.3.1 vendor id (offset 01hC00h) . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.3.2 device id (offset 03hC02h) . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.3.3 command (offset 05hC04h) . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.4 status (offset 07hC06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.5 revision id (offset 08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.3.6 programming interface (offset 09h) . . . . . . . . . . . . . . . . . 7-8 7.3.7 sub class code (offset 0ah) . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.8 base class code (offset 0bh) . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.9 cache line size (offset 0ch) . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.10 latency timer (offset 0dh) . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.11 header type (offset 0eh) . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.12 built-in self test (bist) (offset 0fh) . . . . . . . . . . . . . . . 7-10 7.4 cache control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.4.1 cache control register 1 (offset 50h) . . . . . . . . . . . . . . 7-11 7.4.2 cache control register 2 (offset 51h) . . . . . . . . . . . . . . 7-12 7.4.3 non-cacheable control register (offset 52h) . . . . . . . . 7-13 7.4.4 system performance control register (offset 53h) . . . . 7-14 7.4.5 non-cacheable region #1 (offset 55hC54h) . . . . . . . . . . 7-15 7.4.6 non-cacheable region #2 (offset 57hC56h) . . . . . . . . . . 7-15 7.5 dram control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.5.1 dram configuration register #1 (offset 58h) . . . . . . . 7-16 7.5.2 dram configuration register #2 (offset 59h) . . . . . . . 7-17 7.5.3 dram bank 0 ending address (offset 5ah) . . . . . . . . . 7-19 7.5.4 dram type (offset 60h) . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.5.5 shadow ram control register #1 (offset 61h) . . . . . . . 7-21 7.5.6 shadow ram control register #2 (offset 62h) . . . . . . . 7-21 7.5.7 shadow ram control register #3 (offset 63h) . . . . . . . 7-22 7.5.8 dram timing (offset 64h) . . . . . . . . . . . . . . . . . . . . . . . . 7-23 7.5.9 dram control register #1 (offset 65h) . . . . . . . . . . . . . 7-24 7.5.10 dram control register #2 (offset 66h) . . . . . . . . . . . . . 7-25
vi table of contents AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 7.5.11 32-bit dram width control register (offset 67h) . . . . 7-26 7.5.12 dram refresh counter (offset 6ah) . . . . . . . . . . . . . . . 7-27 7.5.13 dram refresh control register (offset 6bh) . . . . . . . . 7-27 7.5.14 sdram control register (offset 6ch) . . . . . . . . . . . . . . 7-28 7.5.15 dram drive strength control register (offset 6dh) . . 7-29 7.5.16 ecc control register (offset 6eh) . . . . . . . . . . . . . . . . . 7-30 7.5.17 ecc status register (offset 6fh) . . . . . . . . . . . . . . . . . . 7-31 7.6 pci bus control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 7.6.1 pci buffer control register (offset 70h) . . . . . . . . . . . . 7-32 7.6.2 processor-to-pci flow control register #1 (offset 71h) 7-33 7.6.3 processor-to-pci flow control register #2 (offset 72h) 7-35 7.6.4 pci target control register (offset 73h) . . . . . . . . . . . . 7-37 7.6.5 pci initiator control register (offset 74h) . . . . . . . . . . 7-38 7.6.6 pci arbitration control register #1 (offset 75h) . . . . . 7-39 7.6.7 pci arbitration control register #2 (offset 76h) . . . . . 7-40 8 electrical data 8-1 8.1 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 9 switching characteristics 9-1 9.1 clk switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 valid delay, float, setup, and hold timings . . . . . . . . . . . . 9-4 9.3 processor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.4 pci interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.5 dram interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.6 l2 cache timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
table of contents vii 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 10 i b i s models 10-1 10.1 selectable drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 i/o buffer model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3 i/o model application note . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.4 i/o buffer ac and dc characteristics . . . . . . . . . . . . . . . . . 10-3 10.5 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 11 pin descriptions 11-1 11.1 electrical considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 12 package specifications 12-1
viii table of contents AMD-640 system controller data sheet 21090c/0june 1997 preliminary information
list of figures ix 21090c/0june 1997 AMD-640 system controller data sheet preliminary information list of figures figure 1-1. AMD-640 chipset system block diagram . . . . . . . . . . . . . . . 1-4 figure 2-1. AMD-640 system controller block diagram . . . . . . . . . . . . 2-3 figure 2-2. memory-to-pci buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 figure 2-3. pci-to-memory buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 figure 5-1. posted write buffer organization . . . . . . . . . . . . . . . . . . . . . 5-2 figure 5-2. read buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 figure 5-3. 8-bit tag cache connections . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 figure 5-4. cache state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 figure 5-5. pipelined burst read cycle . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 figure 5-6. pipelined burst write cycle. . . . . . . . . . . . . . . . . . . . . . . . . 5-12 figure 5-7. edo dram interface example . . . . . . . . . . . . . . . . . . . . . . 5-16 figure 5-8. sdram interface example . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 figure 5-9. refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 figure 5-10. pipelined edo read (5-2-2-2, 3-2-2-2) . . . . . . . . . . . . . . . . . 5-23 figure 5-11. edo posted write (2-2-2-2) . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 figure 5-12. sdram burst read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 figure 5-13. sdram write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 figure 5-14. cpu read miss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 figure 5-15. read miss with modified l2 cache line . . . . . . . . . . . . . . 5-29 figure 5-16. basic pci read operation . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 figure 5-17. pci burst read operation . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 figure 5-18. pci write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 figure 5-19. pci burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 figure 5-20. configuration write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 figure 5-21. configuration read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 figure 5-22. processor read from pci target . . . . . . . . . . . . . . . . . . . . . 5-38 figure 5-23. processor write to pci target . . . . . . . . . . . . . . . . . . . . . . . 5-39 figure 5-24. pci bus initiator read: cache miss . . . . . . . . . . . . . . . . . . 5-41 figure 5-25. pci bus initiator read: modified l1 hit, l2 miss . . . . . . . 5-43 figure 5-26. pci bus initiator read: l1 miss, unmodified l2 hit . . . . 5-44 figure 5-27. pci bus initiator read: modified l1 hit . . . . . . . . . . . . . . 5-45 figure 5-28. pci bus initiator write: cache miss . . . . . . . . . . . . . . . . . . 5-46 figure 5-29. pci bus initiator write: l1 hit, l2 miss . . . . . . . . . . . . . . . 5-47 figure 5-30. pci bus initiator write: l1 miss, unmodified l2 hit . . . . 5-48 figure 5-31. pci bus initiator write: modified l1 hit, l2 hit. . . . . . . . 5-49 figure 5-32. pci bus initiator write: l1 miss, modified l2 hit . . . . . . 5-50 figure 9-1. clk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 figure 9-2. setup, hold, and valid delay timing diagram . . . . . . . . . . 9-4 figure 12-1. 328-pin bga package preliminary specification. . . . . . . . 12-2
x list of figures AMD-640 system controller data sheet 21090c/0june 1997 preliminary information
list of tables xi 21090c/0june 1997 AMD-640 system controller data sheet preliminary information list of tables table 5-1. common 8-bit tag configurations . . . . . . . . . . . . . . . . . . . . . . 5-6 table 5-2. writeback configurations for 7-bit tag with modify bit . . . . 5-7 table 5-3. cache hit action taken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 table 5-4. cache miss action taken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 table 5-5. cache states vs. bit conditions . . . . . . . . . . . . . . . . . . . . . . . . 5-9 table 5-6. srams vs. bus speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 table 6-1. configuration space header registers . . . . . . . . . . . . . . . . . . 6-1 table 6-2. configuration space cache control registers . . . . . . . . . . . . 6-2 table 6-3. configuration space dram control registers. . . . . . . . . . . . 6-3 table 6-4. configuration space pci control registers . . . . . . . . . . . . . . 6-4 table 7-1. configuration port register summary . . . . . . . . . . . . . . . . . . 7-2 table 7-2. configuration space header registers . . . . . . . . . . . . . . . . . . 7-3 table 7-3. configuration space cache control registers . . . . . . . . . . . . 7-3 table 7-4. configuration space dram control registers. . . . . . . . . . . . 7-4 table 7-5. configuration space pci control registers . . . . . . . . . . . . . . 7-5 table 7-6. mapping host address lines to memory address lines . . . 7-18 table 7-7. ending address register settings . . . . . . . . . . . . . . . . . . . . . 7-19 table 7-8. cas# pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 table 7-9. pbsram timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 table 7-10. functions of pins n17 and m17 . . . . . . . . . . . . . . . . . . . . . . . 7-29 table 7-11. pci burst control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 table 8-1. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 table 8-2. operating ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 table 8-3. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 table 8-4. typical and maximum power dissipation . . . . . . . . . . . . . . . . 8-4 table 9-1. hclk switching characteristics for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 table 9-2. hclk switching characteristics for 60-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 table 9-3. pclk switching characteristics for 33-mhz pci bus . . . . . . 9-3 table 9-4. processor cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 table 9-5. pci interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 table 9-6. dram interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 table 9-7. l2 cache timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 table 11-1. functional grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 table 11-2. AMD-640 system controller pin diagram (top view) . . . . . 11-4 table 12-1. 328-pin bga package preliminary specification . . . . . . . . . 12-1
xii list of tables AMD-640 system controller data sheet 21090c/0june 1997 preliminary information
features 1-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 1features the AMD-640? chipset is a highly integrated system solution that delivers superior performance for the amd-k5? processor, amd-k6? mmx? enhanced processor, and other socket 7-compatible processors. the AMD-640 chipset consists of the AMD-640 system controller in a 328-pin bga package and the amd-645tm peripheral bus controller in a 208-pin pqfp package. the AMD-640 system controller features the 64-bit socket 7 interface, integrated writeback cache controller, system memory controller, and pci bus controller. this document describes the features and operation of the AMD-640 system controller. for a description of the amd-645 peripheral bus controller, see the amd-645 peripheral bus controller data sheet , order# 21095a. key features of the AMD-640 system controller are provided in this section. 1.1 processor interface n supports all 64-bit amd-k5 processors and amd-k6 processors n operates at processor bus speeds up to 66 mhz n supports processors with internal (l1) writeback cache write allocate feature n supports processor bus na# pipeline protocol n low voltage 3.3-v processor interface n system management interrupt, memory remap, and stpclk# 1.2 integrated cache controller n direct-mapped writeback or writethrough secondary cache n global write enable to support pipelined burst synchronous sram (pbsram) cache access n flexible cache size 0, 256 kbytes, 512 kbytes, 1 mbyte, and 2 mbytes
1-2 features AMD-640 system controller data sheet 21090c/0june 1997 preliminary information n 32-byte line size compatible with l1 cache n integrated 10-bit tag comparator n 3-1-1-1 read/write timing for pbsram access at 66 mhz n 3-1-1-1-1-1-1-1 back-to-back read timing for pbsram access at 66 mhz n sustained three-cycle access to pbsram, dram write buffer, and pci write buffer at 66 mhz n data streaming for simultaneous primary and secondary cache line fills n cacheable, write-protected system and video bios n programmable cacheable region and cache timing 1.3 integrated memory controller n supports the following combination of dram types: ? fast page mode (fpm), extended data out (edo), and synchronous dram (sdram) ? 1-, 2-, 4-, and 16-mbit by n-bit drams in one to six banks up to a total of 768 mbytes ? 32-bit and 64-bit data widths ? flexible row and column addressing n 3.3-v and 5-v operation with no external buffers n bank-by-bank error correcting code options n two interleave options: ? two-bank interleaving for 16-mbit sdrams ? two- and four-bank interleaving for 64-mbit sdrams n four cache lines (16 quadwords) of processor-to-dram posted write buffers with full read-around and combine- and-store capability n concurrent dram writeback, read-around-write, and speculative dram read ahead n burst reads and writes n supports the following timings using 60 ns dram: ? edo drams on a 50-mhz or 60-mhz bus: 4-2-2-2 on-page, 7-2-2-2 start-page, and 9-2-2-2 page-miss
features 1-3 21090c/0june 1997 AMD-640 system controller data sheet preliminary information ? edo drams on a 66-mhz bus: 5-2-2-2 on-page, 8-2-2-2 start-page, 11-2-2-2 page-miss, and 5-2-2-2-3-2-2-2 back-to-back access n -15 sdrams on a 60-mhz bus, cas latency = 2: 5-1-1-1 on-page, 8-1-1-1 start-page, 10-1-1-1 page-miss, and 5-1-1-1-3-1-1-1 back-to-back access n -12/-10 sdrams on a 100-mhz bus, cas latency = 3: 6-1-1-1 on-page, 9-1-1-1 start-page, 11-1-1-1 page-miss, and 6-1-1-1-3-1-1-1 back-to-back access n supports bios shadowing on 16-kbyte boundaries n decoupled and burst dram refresh with staggered ras timing n provides the following refresh options: ? programmable refresh rate ? cas-before-ras ? populated banks only 1.4 pci bus controller n support for five pci masters n 32-bit 3.3-v and 5-v pci interface n synchronous pci bus operation up to 33 mhz n pci initiator snoop-ahead and snoop filtering n pci initiator peer concurrence n automatic processor-to-pci burst cycle detection n five-doubleword processor-to-pci post write buffer n 48-doubleword pci-to-dram post write buffer (16 + 32) n 26-doubleword dram-to-pci prefetch buffer (10 +16) n byte merging on processor-to-pci posted writes to reduce the number of pci write cycles n zero wait state pci initiator and target burst transfers n pci-to-dram data streaming up to 132 mbytes per second n full compliance with pci bus specification, revision 2.1 n enhanced pci command optimization (mrl, mrm, mwi) n timer-enforced fair arbitration between pci initiators
1-4 features AMD-640 system controller data sheet 21090c/0june 1997 preliminary information figure 1-1. AMD-640 chipset system block diagram ethernet southbridge l2 cache dram pci bus isa usb system management lan scsi 64-bit 64-bit host bus 32-bit 16-bit dram memory bus serr# preq# pgnt# eide system controller x-bus 8-bit bios amd-k6 processor AMD-640 system controller amd-645 peripheral bus controller
overview 2-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 2 overview the AMD-640 system controller optimizes the interaction between the processor, optional synchronous l2 cache, dram, and the pci bus with pipelined burst and concurrent transactions. it provides 3-1-1-1-1-1-1-1 timing for both read and write transactions with pipelined burst synchronous srams running at 66 mhz. the AMD-640 system controller includes four cache lines (16 quadwords) of processor-to-dram or cache-to-dram write buffering with concurrent writeback capability to accelerate writeback and write miss cycles. 2.1 system the local bus is a non-multiplexed bus based on amd and intel processors. the AMD-640 system controller is capable of performing i/o, single memory, and block memory transactions. the AMD-640 system controller memory controller can perform zero wait state memory reads and writes using an advanced data buffering design. however, in the event of a buffer miss, the memory controller inserts wait states using the brdy# wait procedure. the controller responds only to i/o cycles within its configuration register space and memory requests as defined in its configuration registers. all cycle timing on the local bus is derived from the cpu clock (cclk). this same signal drives the AMD-640 system controller host clock (hclk) input, from which the controller derives all of its timing. the AMD-640 system controller incorporates a high- performance, flexible 64-bit dram controller that provides the dram interface for either an amd-k5 or amd-k6 processor. the memory controller can perform zero wait state reads or writes through the use of a prefetch read buffer or a deep write buffer, respectively. it can address up to six banks of drams in various combinations of 1 mbit, 2 mbit, 4 mbit, and 16 mbit by 32 or 64 bits, up to a total of 768 mbytes. the dram can be any combination of fast page mode (fpm) dram, extended data out (edo) dram, and synchronous dram (sdram). synchronous dram allows zero wait state
2-2 overview AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bursting between the dram and the controllers internal data buffers at 66 mhz. the dram controller can be configured to implement error correction code (ecc) data integrity checking. the bios must determine the type of memory installed and program the configuration registers accordingly. the AMD-640 system controller supports shadowing to accelerate video and system bios accesses. the shadow ram can also be configured to be cacheable and write-protected. the unused portion of dram can be relocated to increase overall system size. in addition, the AMD-640 system controller can be programmed to perform writes to flash eprom, enabling field bios upgrades. the AMD-640 system controller is fully compatible with the pci local bus specification, revision 2.1 . it can operate at either 3.3 v or 5 v, and offers 64-bit to 32-bit data conversion. a five- doubleword posted write buffer enables concurrent processor and pci operation. consecutive processor addresses are converted into burst pci cycles with byte-merging capability for optimal processor-to-pci throughput. a 48-doubleword pci post write buffer and a 32-doubleword pci prefetch buffer facilitate concurrent pci, dram, and cache transactions. enhanced pci bus commands such as memory-read-line, memory-read-multiple, and memory-write-invalid maximize data throughput. the AMD-640 system controller employs a variety of techniques to minimize pci initiator read latency and dram access, including snoop ahead, snoop filtering, forwarding l1 writebacks to the pci initiator, and merging l1 writebacks into the pci posted write buffers. these techniques minimize pci initiator read latency and dram utilization. the combination of these features allows a pci initiator to achieve the full 133-mbyte burst transfer rate. figure 2-1 illustrates the full complement of features and functions built into the AMD-640 system controllers system logic. the configuration of the AMD-640 system controller can be programmed via i/o-mapped configuration registers. a pci- to-cpu read buffer can assemble up to eight bytes of data. a five-doubleword cpu-to-pci write buffer allows the processor to post up to five writes without adding delay on the local bus for pci to complete the cycles. a 26-doubleword dram-to-pci read buffer enables the controller logic to prefetch data, eliminating stalls on pci while waiting for data from dram. a
overview 2-3 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 48-doubleword pci-to-dram write buffer allows pci initiators to post writes to memory without adding delay on either the pci or processor bus. in addition, the AMD-640 system controller contains a pci arbiter. figure 2-1. AMD-640 system controller block diagram dram control byte merge logic 5-doubleword cpu-to-pci write buffer 16-doubleword pci buffer processor interface pci interface cache control ha[31:3] hd[63:0] ads# ahold be[7:0]# brdy# boff# cache# d/c# eads# hitm# hlock# ken#/inv m/io# na# smiact# w/r# ad[31:0] c/be[3:0]# devsel# frame# irdy# lock# par preq# gnt[3:0]# pgnt# req[3:0]# serr# stop# trdy# cas[7:0]#/ dqm[7:0]# ma[13:0] md[63:0] mpd[7:0] ras[5:0]#/ cs[3:0]# bwe# cads# cadv# ce1# coe# gwe# ta[9:0] hclk pclk reset# tagwe# 10 doubleword dram read buffer 4-cache line (32-doubleword) dram write buffer 2 doublewords pci read, cache hit, or writeback forward we[c:a]# scas[c:a]# sras[c:a]#
2-4 overview AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 2.2 AMD-640 system controller buffers figure 2-2 and figure 2-3 show the basic construction of the buffers in the AMD-640 system controller. figure 2-2 shows a path from a 64-bit bus to a 32-bit bus (memory-to-pci). figure 2-3 shows a path from a 32-bit bus to a 64-bit bus (pci-to- memory). the control logic assembles 32-bit words into 64-bit words or disassembles 64-bit words into 32-bit words. figure 2-2. memory-to-pci buffer figure 2-3. pci-to-memory buffer 32 bits 32 bits control memory bus 64 bits 1 quadword n multiplex pci bus 32 bits control pci bus 64 bits 1 quadword n multiplex 64 bits memory bus 32 bits
overview 2-5 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 2.3 definitions, conventions, and references n active-low signalssignal names containing a pound sign, such as ads#, indicate active-low signals. they are asserted in their low-voltage state and negated in their high-voltage state. n reserved bits and signalssignals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descriptions. these bits and signals are reserved by amd for future implementations. when software reads registers with reserved bits, the reserved bits must be masked. when software writes such registers, it must first read the register and change only the non- reserved bits before writing back to the register. n three-statein timing diagrams, signal ranges that are high impedance are shown as a straight horizontal line half- way between the high and low levels. n invalid and dont carein timing diagrams, signal ranges that are invalid or don't care are filled with a screen pattern.
2-6 overview AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 2.3.1 data n quantitiesa word is two bytes (16 bits), a dword or doubleword is four bytes (32 bits), and a qword or quadword is eight bytes (64 bits). n addressingmemory is addressed as a series of bytes on eight-byte (64-bit) boundaries, in which each byte can be separately enabled. n abbreviationsthe following notation is used for bits and bytes: ? kilo k........as in 4 kbytes/page ? mega m......as in 4 mbits/sec ? giga g.......as in 4 gbytes of memory space n little-endian conventionthe byte with the address xx...xx00 is in the least-significant byte position (little end). in byte diagrams, bit positions are numbered from right to left: the little end is on the right and the big end is on the left. data structure diagrams in memory show small addresses at the bottom and high addresses at the top. when data items are aligned, bit notation on a 64-bit data bus maps directly to bit notation in 64-bit-wide memory. because byte addresses increase from right to left, strings appear in reverse order when illustrated. n bit rangesin a range of bits, the highest and lowest bit numbers are separated by a dash, as in 63C00. n bit valuesbits can either be set to 1 or cleared to 0. n hexadecimal and binary numbersunless the context makes interpretation clear, hexadecimal numbers are followed by an h, binary numbers are followed by a b, and decimal numbers are followed by a d.
overview 2-7 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 2.3.2 related publications the following books discuss various aspects of computer architecture that may be useful for your understanding of amd products: amd publications amd-k5 processor data sheet , order# 18522 amd-k5 processor technical reference manual , order# 18524 amd-k6 mmx enhanced processor data sheet , order# 20695 amd-645 peripheral bus controller data sheet , order# 21095 bus architecture pci local bus specification, revision 2.1 , pci special interest group, hillsboro, oregon, 1993. at bus design , edward solari, ieee p996 compatible, annabooks, san diego, ca, 1990. x86 architecture programming the 80386 , john crawford and patrick gelsinger, sybex, san francisco, 1987. 80x86 architecture & programming , rakesh agarwal, volumes i and ii, prentice-hall, englewood cliffs, nj, 1991. general references computer architecture , john l. hennessy and david a. patterson, morgan kaufman publishers, san mateo, ca, 1990.
2-8 overview AMD-640 system controller data sheet 21090c/0june 1997 preliminary information
ordering information 3-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 3 ordering information amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. contact your amd representative for detailed ordering information. family/core a = plastic ball grid array case temperature package type c = commercial temperature range AMD-640 valid combinations opn package type operating voltage case temperature AMD-640ac 328-pin pbga 4.75 vC5.25 v 70 c notes: 1. valid combinations lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly-released combinations. AMD-640 ac
3-2 ordering information AMD-640 system controller data sheet 21090c/0june 1997 preliminary information
signal descriptions 4-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 4 signal descriptions 4.1 processor interface signals ads# address strobe input ads# indicates to the AMD-640 system controller that a new bus cycle is starting. when ads# is asserted, the AMD-640 system controller latches the address bus and all cycle definition signals corresponding to this bus cycle on the rising edge of hclk. ahold address hold output the AMD-640 system controller asserts ahold off the rising edge of hclk while a pci initiator accesses main memory to perform an inquire cycle. the host processor responds by floating ha[31:3] to allow the AMD-640 system controller to drive the address bus. see the timing diagrams in section 6 for example cycles. be[7:0]# byte enables inputs the AMD-640 system controller samples be[7:0]# to determine the valid data bytes during a write cycle and the requested data bytes during a read cycle. the eight byte enable signals correspond to the eight bytes of the data bus as follows: boff# backoff output the AMD-640 system controller asserts boff# to acquire the host bus during pci-to-dram cycles in order to perform snoop cycles and access the l1 and l2 caches in the event of a cache hit. the processor unconditionally aborts any cycles in n be7#: d[63:56] n be3#: d[31:24] n be6#: d[55:48] n be2#: d[23:16] n be5#: d[47:40] n be1#: d[15:8] n be4#: d[39:32] n be0#: d[7:0]
4-2 signal descriptions AMD-640 system controller data sheet 21090c/0june 1997 preliminary information progress and transitions to a bus hold state by floating the following signals: ? a[31:3] ? cache# ? lock# ? ads# ? d[63:0] ? m/io# ?be[7:0]# ?d/c# ?w/r# these signals remain floated until boff# is negated. brdy# burst ready output the AMD-640 system controller asserts brdy# to the host processor off the rising hclk edge. during a read cycle, asserting brdy# indicates that the data bus is being driven with valid data. during a write cycle, it indicates that the data bus has been latched. cache# cacheable access input the host processor asserts cache# during a cacheable read cycle to indicate that it will perform a burst line fill. it asserts cache# during a cacheable write cycle to indicate that it will perform a burst writeback cycle. when the AMD-640 system controller samples cache# low, it stores processor read or write data in the l2 cache. d/c# data/control input when the AMD-640 system controller samples d/c# low, it generates a command on the c/be[3:0]# pci bus signals in the command phase of processor-to-pci bus cycles. eads# external address strobe output the AMD-640 system controller asserts eads# off the rising hclk edge to snoop each cache line transferred during all pci-to-dram cycles. eads# strobes the snoop address into the l1 cache. on l1 cache hits, the processor invalidates unmodified data during writes, and sources (drives) modified data during pci initiator reads and writes. ha[31:3] host address bus input/output the AMD-640 system controller samples addresses driven by the processor on ha[31:3] during memory and i/o cycles and
signal descriptions 4-3 21090c/0june 1997 AMD-640 system controller data sheet preliminary information forwards them to the pci bus or dram, depending on the address range. during pci-to-dram cycles, the AMD-640 system controller drives the address bus to snoop the processors cache and the l2 cache. hd[63:0] host data bus bidirectional hd[63:0] connects to the host processors 64-bit data bus. each of the eight bytes of data that comprise this bus is qualified by a corresponding byte enable signal (be[7:0]#). hitm# inquire cycle hit to modified line input the AMD-640 system controller samples hitm# to determine if an l1 cache snoop has found a modified line. a low on hitm# indicates that a cache line write by the processor is imminent. hitm# is deasserted after the line is written. hlock# host bus lock input the host processor asserts hlock# to indicate that it requires exclusive access to the local bus during a sequence of bus cycles. when the AMD-640 system controller samples hlock# low, it withholds bus grants to other pci initiators. if a grant has already been issued to a pci initiator, the amd 640 will not assert boff# for l1 snoops. these actions effectively suspend a pci-dram transfer until hlock# is deasserted. ken#/inv cache enable/invalidate output during host processor read cycles, ken#/inv functions as the cache enable signal (ken#), indicating a cacheable address when low and a non-cacheable address when high. ken#/inv is driven off the rising hclk edge. during inquire cycles, ken#/inv functions as the invalidate signal (inv), which determines whether an addressed cache line that is found in the host processors l1 cache transitions to the invalid or shared state. m/io# memory or i/o input the AMD-640 system controller samples m/io# during a bus cycle to determine whether the host processor is addressing
4-4 signal descriptions AMD-640 system controller data sheet 21090c/0june 1997 preliminary information memory or i/o space. when m/io# is high, the AMD-640 system controller enables accesses to dram and the l2 cache. when the access is not targeted to the cache or the dram, the AMD-640 system controller uses m/io# to generate the pci commands on c/be[3:0] during the command phase of cpu-to-pci cycles. na# next address output the AMD-640 system controller asserts na# off the rising hclk edge to indicate to the host processor that it is ready to accept a pipelined address. smiact# system management interrupt acknowledge input when smiact# from the host processor is sampled asserted, it indicates to the AMD-640 system controller that the processor has entered system management mode (smm). if configuration register 63h bit, 1 is set, asserted smiact# redirects memory accesses from 30000h:3ffffh to b0000h:bffffh. accesses to this memory area are passed through to the pci bus when smiact# is high, as this is normally the video buffer area. w/r# write/read input the AMD-640 system controller samples w/r# to determine whether the current processor cycle is a write or a read.
signal descriptions 4-5 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 4.2 pci interface signals ad[31:0] pci address/data bus bidirectional ad[31:0] contain the pci address during the first clock cycle in which frame# is asserted, and contain data during subsequent clock cycles. as an initiator, the AMD-640 system controller drives these lines with the address of the target. as a target, the AMD-640 system controller decodes these lines to determine what area of memory to read or write. c/be[3:0]# pci command/byte enables bidirectional c/be[3:0]# contain the pci command during the first clock cycle that frame# is asserted. these lines serve as byte enable signals for subsequent cycles. devsel# pci device select bidirectional the AMD-640 system controller samples devsel# when it is the initiator in a pci cycle to determine if the target device has responded. the AMD-640 system controller asserts devsel# when it is the targeted device in a pci cycle. frame# pci cycle frame bidirectional the AMD-640 system controller asserts frame# at the beginning of a pci cycle when it is the initiator, and holds it low until the beginning of the last data transfer in the cycle. if the AMD-640 system controller is the targeted pci device, it samples and latches the c/be[3:0]# and ad[31:3] signals and asserts devsel# at the first pclk edge on which it samples frame# asserted. gnt[3:0]# pci bus grant outputs as the pci bus arbiter, the AMD-640 system controller asserts one of these device-specific bus grant signals off the rising clock edge to indicate to an initiator that it has been granted control of the pci bus.
4-6 signal descriptions AMD-640 system controller data sheet 21090c/0june 1997 preliminary information irdy# initiator ready bidirectional irdy# indicates that a pci initiator is ready to complete the current data phase of the transaction. during a read cycle, asserted irdy# indicates the master is ready to accept the data. during a write cycle, asserted irdy# indicates that write data is valid on ad31:ad0. data is transferred on the pci bus on each pclk in which both irdy# and trdy# are asserted. wait states are inserted on the bus until both irdy# and trdy# are asserted together. irdy# is an output when the AMD-640 system controller is the pci initiator. the AMD-640 system controller drives irdy# low one pclk after it asserts frame# and holds it low until one cycle before the end of all transactions. irdy# is an input when the AMD-640 system controller is a pci target. the AMD-640 system controller does not terminate a read or write cycle until it samples both irdy# and trdy# low. lock# pci bus lock bidirectional as a pci initiator, the AMD-640 system controller asserts lock# to prevent other devices from accessing the target device during atomic cpu-to-pci transactions. par pci bus parity bidirectional the AMD-640 system controller drives par as a pci initiator one clock after the address phase and each data write phase to generate even parity across ad[31:3] and c/be3:0]#. it drives par as a pci target one clock after each data read phase. pgnt# pci grant to amd-645 peripheral bus controller output pgnt# is asserted off the rising clock edge and grants control of the pci bus to the pci-isa/ide bridge functions implemented in the amd-645 peripheral bus controller. preq# pci request from amd-645 peripheral bus controller input the AMD-640 system controller samples preq# to determine if the amd-645 peripheral bus controller needs pci bus access.
signal descriptions 4-7 21090c/0june 1997 AMD-640 system controller data sheet preliminary information req[3:0] pci bus request inputs as the pci bus arbiter, the AMD-640 system controller samples these device-specific bus request signals to determine if another agent requires control of the pci bus. serr# system error output a pci agent (the AMD-640 system controller or other device) asserts serr# off the rising clock edge one clock after it detects a system error. serr# is an input to the amd-645 peripheral bus controller, which can be programmed to generate an nmi. stop# pci bus stop input as a pci initiator, the AMD-640 system controller samples stop# to determine if the target device requires it to abort or retry a transaction. trdy# target ready bidirectional as a pci initiator, the AMD-640 system controller samples trdy# to determine when the target agent is able to complete the data phase of a transaction. as a pci target, the AMD-640 system controller asserts trdy# to indicate that it has latched the data on ad31:ad0 during a write phase or driven data on ad31:ad0 during a read phase.
4-8 signal descriptions AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 4.3 dram interface signals cas[7:0]#/ dqm[7:0]# column address strobe/ outputs data mask cas[7:0]# generate column address strobes for fpm and edo dram during processor-to-dram and pci-to-dram cycles. cas7# connects to the most-significant byte of each bank, and cas0# connects to the least-significant byte. the width and delay of these signals are adjustable. for sdram, these lines function as data masks dqm[7:0]# for each byte during sdram write cycles. ma[13:0] memory address outputs the multiplexed row and column address bits ma[13:0] connect to the system drams. they can address any size dram from 256 kbits to 16 mbits by n bits. md[63:0] memory data bidirectional md[63:0] connect to the dram data bus. they are driven by the dram when reading. they are driven by the AMD-640 system controller during writes. mpd[7:0] memory ecc bidirectional mpd[7:0] carry error correction codes for the eight bytes of data on md[63:0]. they are inputs to the AMD-640 system controller during dram read cycles and outputs during dram write cycles. ras[5:0]#/ cs[5:0]# row address strobe 5:0/ outputs chip selects 5:0 ras[5:0]# generate row address strobes for the dram banks, either during cpu-to-dram or pci-to-dram accesses or in sequence during dram refresh cycles. cs[5:0]# function as chip select lines for sdrams if bits 5C4 in configuration register 60h select sdram.
signal descriptions 4-9 21090c/0june 1997 AMD-640 system controller data sheet preliminary information scasa#, scasb#, scasc# synchronous dram outputs column address strobe scasa#, scasb#, and scasc# are column address strobe pins for synchronous dram. they operate in parallel to drive greater loads than a single pin can support. srasa#, srasb#, srasc# synchronous dram outputs row address strobe srasa#, srasb#, and srasc# are row address strobe pins for synchronous dram. they operate in parallel to drive greater loads than a single pin can support. wea# web# wec# synchronous dram outputs memory write enable wea#, web#, and wec# are write enable pins for all dram. they operate in parallel to drive greater loads than a single pin can support.
4-10 signal descriptions AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 4.4 cache controller interface signals bwe# byte write enable output bwe# connects to the bwe# input on each of the l2 cache srams. when the AMD-640 system controller l2 cache controller asserts bwe# off the rising clock edge during cache writes, data on the processor bus (d[63:0]) is written to those bytes of the cache sram whose byte-enable lines (be[7:0]#) are asserted. cads# cache address strobe output the AMD-640 system controller normally drives cads# high. it enables cads# to be asserted when it acquires the host processor bus by asserting boff#, and asserts cads# off the rising clock edge during pci-to-dram cycles that hit the l2 cache. cadv# cache advance output cads# connects to the ads# inputs of the l2 cache srams. the AMD-640 system controller asserts cads# off the rising clock edge during l2 cache line read and write hits as well as during line fills and line writebacks, incrementing the srams internal counters to advance to the next quadword in the cache line. ce1# chip enable 1 output the ce1# chip select signal enables the l2 cache for both reads and writes. it is asserted off the rising clock edge. coe# cache sram output enable output the AMD-640 system controller asserts coe# off the rising clock edge of a cache read hit or writeback cycle and holds it low for the duration of the cycle to enable cache sram output. it also asserts coe# during the first two clock cycles of cpu-to- pci memory reads, non-cacheable reads, or read misses without writeback.
signal descriptions 4-11 21090c/0june 1997 AMD-640 system controller data sheet preliminary information gwe# global write enable output gwe# connects to the global write inputs of the cache srams. the AMD-640 system controller asserts gwe# off the rising clock edge during l2 cache line fills to enable the srams to receive each quadword of the line being returned by the dram controller. ta[9:0] tag address bidirectional ta[9:0] are used to read and write the cache page number to and from external tag ram. they function as outputs during l2 cache line fills and as inputs at all other times. tagwe# tag write enable output the AMD-640 system controller asserts tagwe# on the rising edge of hclk to enable the l2 cache tag srams to receive the next tag address.
4-12 signal descriptions AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 4.5 clocks and reset hclk host clock input hclk receives a buffered host clock. it is used by all of the AMD-640 system controller logic in the host clock domain. it is the primary reference for all bus cycles on the processor and memory buses as well as most of the internal logic. pclk pci clock input pclk receives a buffered host clock divided by two. it is used by all of the AMD-640 system controller logic in the pci clock domain. reset# reset input asserting reset# resets the AMD-640 system controller and sets all register bits to their default values. bidirectional pins are three-stated and outputs are driven inactive. this signal is driven by the pcirst# signal from the amd-645 peripheral bus controller.
functional operation 5-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 5 functional operation 5.1 processor interface the AMD-640 system controller responds to cpu-generated bus signals and activates the pci, dram, and cache state machines according to the command type and address range. on memory cycles it drives the processor address onto the memory bus from its integrated dram controller. for pci target cycles it drives the pci bus from its integrated pci buffers and control logic. the AMD-640 system controller maintains coherency of the processor primary (l1) cache with the rest of the system using the ken#, eads#, and hitm# pins. it monitors the cache# signal from the processor to determine burst cycles and returns ken# asserted when data is cacheable. ken# is normally active during a memory read cycle unless the processor address lies outside the cacheable region. in this case, the AMD-640 system controller deasserts ken# before the completion of the first burst transfer so that the data is not written to the l1 cache. the AMD-640 system controller does not write data to the secondary (l2) cache when cache# is inactive unless it is programmed to do so by setting bit 2 of register 52h. it asserts the eads# signal during dma and pci initiator cycles to snoop the l1 cache. the processor responds to a cache hit by asserting the hitm# line. this action notifies the AMD-640 system controller that a modified cache line must be written back to the system before the intended memory access can be performed. a snoop filtering mechanism in the AMD-640 system controller minimizes snoop overhead by ensuring that consecutive accesses to the same cache line are snooped only once. 5.1.1 write posting the AMD-640 system controller contains four write buffers to enhance memory write performance. each buffer can hold one entire cache line, also referred to as a data block, which is 32
5-2 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bytes (four quadwords). the write buffers are always enabled. the memory controller supports both single and block writes. block writes are more common in a typical system than single writes because most processors use writeback caches, which transfer data in blocks. when a writeback cache is employed, the AMD-640 system controller sees a block transaction every time the processor clears a cache line. the controllers posted write buffers can handle four back-to-back block transactions without wait states. figure 5-1 shows how the posted write buffers are organized. figure 5-1. posted write buffer organization the write buffers are organized as pseudo fifo (first-in-first- out) buffers, i.e. writes from the buffers to memory are performed in the order they are received from the processor. four consecutive write transactions, whether single or block, will fill all four 32-byte buffers. write buffers continue to accept data until either the buffers are full or all data from the processor has been received, at which point the controller begins writing data to the dram. as each pending write to main memory is performed, freeing the corresponding buffer, write control logic processor address bus processor data bus memory data bus buffer 1 address tag buffer 2 address tag buffer 3 address tag buffer 4 address tag buffer 1 data 32 bytes buffer 2 data 32 bytes buffer 3 data 32 bytes buffer 4 data 32 bytes
functional operation 5-3 21090c/0june 1997 AMD-640 system controller data sheet preliminary information the memory controller will assert brdy# to accept another block from the processor if one is pending. each write buffer has its own address tag bits, which are compared to the address on the processor address bus. in a write cycle, the comparators determine the next buffer (if any) available to accept processor data. in a read cycle, the comparators are used to snoop the write buffers to maintain data coherency. if a read address matches one of the write buffer address tags (buffer hit), the read cycle is stalled by deasserting brdy# until the write to memory is retired. if no match occurs, a read around write can be performed (page 5-5). 5.1.2 read buffer the AMD-640 system controller contains five 8-byte read buffers, each of which can hold an entire 64-bit word of data. the buffers are designed to increase memory read performance by prefetching data from the main memory and supplying the data to the processor with zero wait states. the read buffers are organized in a manner similar to a five- way set-associative cache, with the set-associativity dictated by an address affinity. each of the read buffers has it's own address tag bits. on every read cycle, the address being requested is compared to the addresses of the read buffer lines. figure 5-2 shows how the read buffers are organized. if one of the buffers contains a requested quadword address, the data is presented to the processor with zero wait states and the next quadword is then prefetched into the same buffer. if no buffer contains the quadword, the controller reads it and the next quadword from memory into the read buffer. for a block read cycle, the next line (four quadwords) of data is prefetched into the read buffer.
5-4 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information figure 5-2. read buffers memory reads that fill the processor's caches are by far the most common types of reads. these reads occur as a burst read of four quadwords (32 bytes). when a burst read hits in the controllers read buffer, the transactions are identical to the single qword read described above except that the brdy# signal is extended for three more clocks and, following the first qword transfer, three more quadwords of data are output onto the data bus at the rate of one quadword per clock. thereafter, subsequent blocks that access sequential locations are all prefetch-queue hits because the memory controller fills the read queue as an integral part of the read cycle. the read buffers snoop write transactions to maintain data coherency. if a write transaction occurs to an address whose data is contained in one of the read buffers, that read buffer is invalidated. read control logic processor address bus processor data bus memory data bus buffer 1 address tag buffer 2 address tag buffer 3 address tag buffer 4 address tag buffer 1 data 8 bytes buffer 2 data 8 bytes buffer 3 data 8 bytes buffer 4 data 8 bytes buffer 5 data 8 bytes buffer 5 address tag
functional operation 5-5 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 5.1.3 read-around-writes this feature minimizes processor stalling by interrupting a write in progress to service a processor read, effectively giving read priority over write. the dram controller finishes writing the current word, reads the desired data into the cpu read buffer, then continues the write from the post write buffer. in the special case of a read to an address contained in the post write buffer, the read will not proceed until the write has completed. read-around-write is enabled by bit 7 of offset 53h. 5.2 cache controller the AMD-640 system controller supports direct-mapped cache systems with data sizes ranging from 128 kbytes to 2 mbytes. it can accommodate both synchronous and asynchronous data srams to provide flexibility for system trade-offs between cost and performance. either writeback or writethrough cache schemes are available, and writeback can be implemented with or without a modify bit. if no modify bit is used in a writeback scheme, all lines are treated as modified. this scheme offers a larger cacheable region (compare table 5-1 and table 5-2) but does not perform as well as one with a modify bit. 5.2.1 cache organization the configuration of tag lines ta[9:0] determines the l2 cache size and address range. most l2 cache schemes employ 8-bit tags, in which case only the lower eight tag lines are used. the size of the cache determines the particular address lines to which ta[7:0] correspond. table 5-1 shows some typical 8-bit tag configurations.
5-6 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information figure 5-3 shows how the AMD-640 system controller connects to a typical 8-bit tag cache. . figure 5-3. 8-bit tag cache connections table 5-1. common 8-bit tag configurations cache size ta[7:0] tag size tag ram address cacheable region 256 kbytes a[25:18] 8kx8 a[17:5] 64 mbytes minus cache size 512 kbytes a[26:19] 16kx8x2 a[18:5] 128 mbytes minus cache size 1 mbyte a[27:20] 32kx8 a[19:5] 256 mbytes minus cache size 2 mbytes a[28:21] 32kx8x2 a[20:5] 512 mbytes minus cache size ha[17:5] ha[17:3] hd[63:0] coe# cache a[12:0] ta[7:0] tagwe# comparator cache size = 256k ha[27:18] cache write cpu address bus sram cache tag sram register offset 51h bits 1C0 = 00 mux cpu data bus a[25:18] AMD-640 system controller
functional operation 5-7 21090c/0june 1997 AMD-640 system controller data sheet preliminary information the AMD-640 system controller can support a 9-bit or 10-bit tag ram by enabling ta9 and ta8 in configuration register 50h. refer to section 7.4.1 on page 7-11. ta8 extends the cacheable region to one gigabyte. ta9 extends it to two gigabytes. alternatively, ta7 can be programmed to function as a modify bit, as shown in table 5-2. . 5.2.2 cache operation the AMD-640 system controller contains an integrated 10-bit cache tag comparator which is active during every cache access cycle from either the processor or a pci initiator. it compares the command address with the tag sram to determine if the cycle is a cache hit or cache miss. cache hits the action taken on a cache read hit is the same for all cache schemes, but varies for different schemes on a cache write hit. in the writethrough scheme the AMD-640 system controller writes data to dram immediately when a cache line is modified. in the writeback scheme employing a modify bit, the AMD-640 system controller merely sets the modify bit of the altered cache line when a line is modified. on a pci cycle, the AMD-640 system controller snoops the processors l1 cache. if it contains the desired pci data and it has been modified, the cache line must be written back. however, the writeback forwarding feature allows the pci initiator to read the cache data before the writeback takes place. processor writeback cycles are handled as normal processor write cycles. table 5-3 shows the actions taken by the AMD-640 system controller on a cache hit cycle. table 5-2. writeback configurations for 7-bit tag with modify bit cache size ta[6:0] tag size tag ram address cacheable region 256 kbytes a[24:18] 8kx8 a[17:5] 32 mbytes minus cache size 512 kbytes a[25:19] 16kx8x2 a[18:5] 64 mbytes minus cache size 1 mbyte a[26:20] 32kx8 a[19:5] 128 mbytes minus cache size 2 mbytes a[27:21] 32kx8x2 a[20:5] 256 mbytes minus cache size
5-8 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information cache misses table 5-4 shows the action taken on a cache miss cycle. the action taken during a cache write miss cycle is identical for most cache schemes, but varies for different schemes on a read miss cycle. a cache line is allocated on a read miss only, not on a write miss. with a writethrough cache, no writeback action is required because dram-cache coherency is always maintained. with a writeback cache, the existing cache line must be written back to dram if its modify bit is set. if no modify bit is employed, the line is assumed to be modified and writeback action is required unless the line is in a write-protected region. processor writeback cycles are handled as normal processor write cycles. on a pci cycle, the AMD-640 system controller snoops the processors l1 cache. if it contains the desired pci data and it has been modified, the cache line must be written back. writeback forwarding allows the pci to read the modified data before it is written back. table 5-3. cache hit action taken cycle type action taken processor read 1. data (all four bytes) are read from cache. 2. cache data, tag, and modify bits are unchanged. processor write 1. data with active byte enables are written to the cache. 2. the tag is unchanged. 3. the modify bit is set (writeback/modify bit scheme only). 4. the data is also written to dram (writethrough scheme only). pci read 1. the processor is snooped to write back modified internal cache line. 2. data (all four bytes) are read from cache. 3. cache data, tag, and modify bits are unchanged. pci write 1. the processor is snooped to write the back modified internal cache line. 2. data with active byte enables are written to the cache. 3. the tag is unchanged. 4. the modify bit is set (writeback/modify bit scheme only). 5. the data is also written to dram (writethrough scheme only).
functional operation 5-9 21090c/0june 1997 AMD-640 system controller data sheet preliminary information protocol to simplify system design, the AMD-640 system controller uses only one cache control bit (the modify bit) rather than the two bits employed in the mesi (modified, exclusive, shared, invalid) protocol. in writeback mode there are only three cache statesinvalid, valid, and modified. the modify bit indicates whether the cache line is valid (cleared) or modified (set), except when all active tag lines are set, which indicates the invalid state. table 5-5 summarizes bit conditions for the various cache states. figure 5-4 shows how cache state transitions occur. table 5-4. cache miss action taken cycle type action taken processor read 1. the line currently in the cache is written back to dram if no modify bit is used or the modify bit is set. 2. the entire data line is read from dram and written to the cache. 3. the tag is updated. 4. the modify bit is reset (writeback/modify bit scheme only). 5. the requested data is returned to the processor. processor write 1. the data is written to dram. 2. cache data, tag, and modify bits are unchanged. pci read 1. the processor is snooped to write back the modified internal cache line. 2. data (all four bytes) are read from dram. 3. cache data, tag, and modify bits are unchanged. pci write 1. the processor is snooped to write back the modified internal cache line. 2. data is written to the cache. 3. cache data, tag, and modify bits are unchanged. table 5-5. cache states vs. bit conditions cache state modify bit other tag lines valid 0 not all 1s modified 1 not all 1s invalid x all 1s
5-10 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information figure 5-4. cache state transitions operating modes the cache controller has three operating modes: enabled, disabled, and initialization. in the enabled mode, the cache controller functions normally. in the disabled mode, all read and write cycles are passed to the dram controller with no change to the cache data and tag bits. the initialization mode puts the cache into a defined state after power-up. the bios puts the cache controller into the initialization state by writing 01 to offset 50h, bits 7-6, then reads from memory to fill the cache with valid data. the reads should start at xx00000 (xx depends on the cache size) and end at the cache limit. this requirement forces all lines to be valid. finally, the bios enables the cache by clearing bits 7-6. the bios normally performs this initialization before the cache is enabled. any software that tests this feature after the cache has been enabled should reside in non-cacheable memory to prevent a system crash. invalid valid cpu read & cache hit & pci write to cpu write cache miss cache hit dram with modified
functional operation 5-11 21090c/0june 1997 AMD-640 system controller data sheet preliminary information figure 5-5 shows a burst read from pbsram. the assertion of coe# indicates an l2 cache hit. cadv# allows the address to increment on each clock. the completion of the data g access is not shown. figure 5-5. pipelined burst read cycle 13 2 addr for data a ab c d addr for data g hclk w/r# ads# na# brdy# ha[31:3] be[7:0]# cadv# cads# ce1# coe# tagwe# ta[9:0] hd[63:0] cache#
5-12 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information figure 5-6 shows a burst write to pbsram. note that cadv#, which allows the address to increment, is high for one clock following ads#. the completion of the data g access is not shown figure 5-6. pipelined burst write cycle 12 3 addr for data a abcd addr for data g hclk w/r# ads# na# brdy# ha[31:3] be[7:0]# cadv# cads# ce1# gwe# bwe# coe# tagwe# ta[9:0] hd[63:0]
functional operation 5-13 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 5.2.3 write buffers the AMD-640 system controller includes cpu-to-dram and pci-to-dram write buffers to improve performance during cache read and write miss cycles. on a cache read hit to a modified line, the buffers allow subsequent cache lines to be read while the altered line is written back to dram. on cache write misses, the AMD-640 system controller asserts the brdy# line, enabling the processor to start the next cycle while the buffered data is written to dram. the AMD-640 system controller also allows reads to bypass pending writes (see section 5.1.3, page 5-5). 5.2.4 cacheable region only dram attached to the AMD-640 system controller is cacheable. the cacheable region is further limited by the following factors: n the size of the dram and cache n the number of tag lines enabled by the cache control 1 configuration register, offset 50h (page 7-11) n the settings in the non-cacheable region configuration registers, offsets 54hC57h (page 7-15) n the cacheability of video and system bios as determined by the shadow ram control configuration registers, offsets 61hC63h (page 7-21) the normal cacheable region is the lesser of the dram size and 256 times the cache size (512 or 1024 if 9 or 10 tag bits, respectively, are used). the normal cacheable region is decoded automatically and does not require setting any configuration registers. within the normal cacheable region, two noncacheable areas can be specified by the non-cacheable region configuration registers (page 7-15). the upper memory region (a0000h to fffffh) is noncacheable by default because it corresponds to the memory-mapped i/o ports. however, the video and system
5-14 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bios (c0000h-c7fffh and e0000h-effffh, respectively) can be made cacheable and write-protected by programming the shadow ram control configuration registers. the ken# and eads# signals maintain consistency in the cacheable region between the l1 and l2 caches. ken# alerts the processor if data being read is cacheable. the eads# signal, which the AMD-640 system controller uses to snoop the l1 cache on pci-dram cycles, is only asserted for data in the cacheable region. 5.2.5 cache parameters data transactions with the l2 cache sram may differ depending on the type of sram selected. this variance implies that a specific sram speed may be required for different bus speeds. examples of sram used for various bus speeds are shown in table 5-6. 5.2.6 cache snooping snoop filtering snoop filtering increases processor bandwidth by reducing the number of snoop cycles (also called inquire cycles) on the local bus. when a pci cycle causes a snoop, the AMD-640 system controller retains the number of the cache line. if a subsequent access addresses the same line, no snoop cycle is generated. snoop ahead read this feature prevents stalling a pci burst transfer to fetch data from dram. in a pci read cycle, the AMD-640 system controller snoops the cache and reads data from there rather than dram if it is present. the controller would then commence a pci burst cycle. however, if the next data line were not in the cache, the controller would have to stall the burst in order to fetch the next line from dram. with snoop table 5-6. srams vs. bus speeds type of sram 60 mhz 66mhz wait states asynchronous 6.7 ns 5 ns 0 synchronous 15 ns 12 ns 0 sync pipelined burst 66 mhz 0
functional operation 5-15 21090c/0june 1997 AMD-640 system controller data sheet preliminary information ahead read, the controller looks at the next cache line before starting the pci burst, thus avoiding this potential loss of time. 5.3 dram controller the AMD-640 system controller supports up to six 64-bit banks of dram with a capacity of up to 768 mbytes. each bank can contain 1-, 2-, 4-, or 16-mbit by 32- or 64-bit drams, in any combination of fpm, edo, or sdram. fpm and edo drams can be 72-pin simms with either 36 bits if error correcting code (ecc) is required, or 32 bits (no ecc). sdram can be 168-pin dimms with either 72 bits (ecc) or 64 bits (no ecc). bank 1 is enabled by ras0#, bank 2 is enabled by ras1#, and so on. single-banked memory modules require one ras# signal and occupy a single row. dual-banked memory modules occupy two rows of memory and require two ras# signals. the dram banks are grouped into three pairs. each pair can have zero, one, or both banks populated. the only constraint is that if both banks in a pair are populated they must be of the same type (size, simm configuration, and mode). all of the dram parameters are programmed in configuration registers 58hC6fh. see pages 7-16 through 7-31.
5-16 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 5.3.1 mixing memory the AMD-640 system controller can accommodate different memory sizes or types in different banks, but not within the same bank or bank pair. configuration registers 58hC6fh are used to program the ending address, column address size, dram type, error correction, timing, refresh interval, drive strength, and width for each bank. rules for populating dram are as follows: 1. pairs must be of the same type (fpm or edo dram). 2. if 64-bit mode is used, the banks must be paired. they need not be paired in 32-bit mode. 3. they must be populated in order. i.e., 0,1,2,3,4,5. figure 5-7 shows how edo dram connects to the AMD-640 system controller. figure 5-8 shows connections to sdram. figure 5-7. edo dram interface example md[63:32] AMD-640 system controller web# wea# cas[7:4] ma[11:0] cas[3:0] 72-pin, 32- or 36-bit dram simm 72-pin, 32- or 36-bit dram simm 72-pin, 32- or 36-bit dram simm 72-pin, 32- or 36-bit dram simm 72-pin, 32- or 36-bit dram simm 72-pin, 32- or 36-bit dram simm ras[5:0]# ras0# ras1# ras2# ras3# ras4# ras5# ma[11:0] md[31:0]
functional operation 5-17 21090c/0june 1997 AMD-640 system controller data sheet preliminary information figure 5-8. sdram interface example scasb# 168-pin, 64- or 72-bit sdram dimm module wec# wea# scasc# scasa# srasa# AMD-640 system controller md[63:0] dqm[7:0]# ma[11:0] cs[5:0]# 168-pin, 64- or 72-bit sdram dimm module 168-pin, 64- or 72-bit sdram dimm module 168-pin, 64- or 72-bit sdram dimm module 168-pin, 64- or 72-bit sdram dimm module 168-pin, 64- or 72-bit sdram dimm module srasc# 0 1 2 3 4 5 scasb# srasb# web#
5-18 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information memory detection the AMD-640 system controller can accommodate different memory sizes or types in different banks, but not within the same bank or bank pair. a software or firmware mechanism can be integrated into the bios that automatically detects the type and size of the dram device in each bank. the mechanism sets the last bank populated to bank 0 (offset 59h bits 2-0, page 7-19), determines its type and size, sets the bank 0 ending address (offset 5ah, page 7-19), increments the last bank populated register, and performs the test on bank 1, making sure the address range for bank 1 is above the range determined for bank 0. the cycle is repeated for all populated banks. to determine the type of device, the mechanism configures the target dram bank as edo, enables it, writes data to it, reads the data back, and compares the results. a match indicates the presence of edo dram, because standard dram does not respond properly to the faster edo access cycles. if the comparison fails, the mechanism configures the bank as fpm dram and performs a similar test. if this test also fails, a somewhat more complex test can be run to determine if sdram is present or a bank is empty. refer to the bios guide for more details. this procedure should be performed on eight consecutive bytes to determine if different types of memory devices are installed within a row. any row containing differing memory types should be disabled. to determine the size of the device, the mechanism sets the start address either at 0 or somewhere in the upper memory area. then, using the memory column size bits in the corresponding configuration register (offsets 58h or 59h), the mechanism selects the largest size and tests the memory at all possible boundaries. 5.3.2 error correction code the AMD-640 system controller supports error correction code (ecc) to check the integrity of transactions with system memory. ecc, also referred to as hamming code, corrects single-bit and double-bit errors as well as some triple-bit errors. ecc is enabled in offset 6eh (page 7-30). the memory modules must have parity bits to implement ecc.
functional operation 5-19 21090c/0june 1997 AMD-640 system controller data sheet preliminary information ecc operation requires that system memory be initialized. in this procedure, the bios writes to every memory location, generating valid ecc that is stored in the dram parity bits. if this procedure is not performed, errors will occur when writing data smaller than a 64-bit doubleword. memory types cannot be mixed when ecc is employed. all memory must be of the same typesdram, fpm, or edo. also, some timing delay should be added to allow for the delay added by the ecc logic. systems using sdram, should set offset 6eh, bit 3 (see page 7-30). with edo or fpm dram, the cas# width in offset 64h, bits 3C2 should be programmed 1t more than normal (see page 7-23). in some cases, the half-cycle delay added by setting offset 65h, bit 3 (see page 7-24) is sufficient. 5.3.3 dram refresh the AMD-640 system controller provides dram refresh that is transparent to the rest of the system. normal, burst, or cas- before-ras (cbr) refresh can be selected through offset 6bh (page 7-27). accesses to the read and posted write buffers are allowed during a refresh period. ras# pulses to the six memory banks are staggered one hclk apart to minimize switching noise during memory refresh, as shown in figure 5-9. figure 5-9. refresh timing hclk ma[13:0] ras0# ras1# ras2# ras3# ras4# ras5# cas[7:0]#
5-20 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information the AMD-640 system controller also contains a refresh counter that provides 4096 refresh cycles on ma[11:0]. this permits the use of drams up to 16 mbits in size. the refresh period is derived by dividing hclk by 16 (four-bit prescale) and a refresh divisor based on the 8-bit value in offset 6ah. the refresh divisor can be calculated by multiplying the drams required refresh period by the prescaled clock rate. for example, in a system with hclk = 66 mhz and 4-mbit dram requiring a refresh interval of 1024 cycles every 16 ms, the refresh divisor would be calculated as follows: refresh divisor = refresh period * prescaled clock = (16x10 -3 sec/1024 cycles) * (66 x 10 6 /16) = 64.5 (decimal) = 42h (hexadecimal) page mode dram the AMD-640 system controller generates dram addresses based on the processor address and type of dram. row and column addresses are multiplexed on the same ma bus. for non-page mode operations and page misses, the AMD-640 system controller sequentially generates a row address and column address. on page hits, only a column address is generated during the dram access. dram cycles normally operate in page mode. in this mode, ras# is held active after a dram access has finished in anticipation of the next access. ras# is brought high to precharge the dram only when a subsequent cycle to the same bank accesses a different dram page or an asynchronous event such as a ras# time-out occurs. with fast page mode drams, the column address is latched on the falling edge of cas#. fpm drams require cas# to stay active throughout the entire cycle, because their drives turn off when cas# goes high. while a page cycle continues within a row, ras# remains active while cas# is toggled as the address (column) changes. fast page mode drams are enabled or disabled for each bank pair in offset 60h (page 7-24). dram cycles for all processor accesses are generated synchronously with the cpu clock (hclk). critical dram timing parameters including ras# precharge time and pulse width, cas# and write pulse widths, and column address-to-
functional operation 5-21 21090c/0june 1997 AMD-640 system controller data sheet preliminary information cas# delay can be individually programmed in configuration register 64h. 5.3.4 shadow ram the AMD-640 system controller supports shadowing of system, video, and other bios functions to accelerate access. the bios normally resides in read only memory (rom) to prevent altering the content of this crucial system code. because rom is substantially slower than ram, most systems provide for copying the rom contents to the upper memory area of ram and making that area read only. the portion of ram containing the bios copy is referred to as shadow ram. the AMD-640 system controller provides three control registers (offset 61hC63h, starting on page 7-21) to select the portions of upper memory for shadowing and to control read/write access to those areas. the granularity is 16 kbytes in the address range c0000hCdffffh and 64 kbytes in the address range e0000hCfffffh. read and write access can be enabled independently in each region. further system performance enhancement can be achieved by programming address ranges c0000hCc7fff and e0000hCfffffh to be cacheable and write-protected. to copy the rom code into the targeted shadow memory, set the access control bits for that area to write only, then copy the rom code (read address) to the shadow memory (write address) with the source and destination pointed to the same physical address. after completion of the copy process, adjust the access control bits to read only. if shadow ram is not enabled, addresses a0000hCfffffh can be relocated to the top of local dram, increasing memory size by 384 kbytes. if only the c segment (c0000hCcffffh) and/or the f segments are used for shadowing, memory is increased by 256 kbytes. no dram can be relocated if either the d or e segment is used for shadow memory. addresses a0000hC bffffh can be reserved for the system management memory map by setting register 63h bit 1 and cannot be relocated again. in this case, memory increases are reduced to 256 kbytes (no shadowing) and 128 kbytes (c and/or f segments used for shadowing).
5-22 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 5.3.5 edo dram edo dram can increase system speed because most edo accesses take one clock cycle less than standard fpm devices. the AMD-640 system controller generates the appropriate clock cycles for fpm or edo based on the information in configuration registers 60h and 64h. edo memory allows shorter page cycle times by keeping the output drivers on when cas# goes inactive. (fast-page drams require cas# to stay active throughout the entire cycle.) the basic characteristics of edo memory are as follows: ? the column-address is latched when cas# falls. ? the output drivers remain on when cas# goes high, and only turn off when both cas# and ras# are deasserted. ? data is valid until either the next falling edge of cas# or the next rising edge of oe#. figure 5-10 shows a pipelined burst read from edo memory, as indicated by the assertion of na#. the first access is 5-2-2-2 and the second is 3-2-2-2. the five clock cycles in the first access indicate a page hit. on a page miss the first access is 11 clock cycles to allow for precharging the row and strobing the new row address into the controller.
functional operation 5-23 21090c/0june 1997 AMD-640 system controller data sheet preliminary information figure 5-10. pipelined edo read (5-2-2-2, 3-2-2-2) col addr a abcd e fgh 123 12345 hclk ads# be[7:0]# na# ha[31:3] brdy# w/r# ma[13:0] ras[5:0]# cas[7:0]# wex# hd[63:0] md[63:0] addr a addr e
5-24 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information figure 5-11 shows a write to address a followed by a pipelined read request from address g. the pipelined read is not shown. the write from the processor to the write buffer is a 3-1-1-1 cycle. the transfer from the buffer to dram does not begin until the entire line is written to the write buffer. the write buffer allows the processor to continue processing much earlier than if the processor was required to wait for the write to dram to complete. figure 5-11. edo posted write (2-2-2-2) abcd abcd addr a addr g write read 12 3 123 begin dram write hclk ads# be[7:0]# na# ha[31:3] brdy# w/r# ma[13:0] ras[5:0] cas[7:0] wex# hd[63:0] md[63:0]
functional operation 5-25 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 5.3.6 synchronous dram synchronous dram is the most recent innovation in the evolution of main memory systems to meet the higher bandwidth needs of todays processors. sdrams use a clock to synchronize address and data rather than row and column strobes. they can also be programmed to select the burst length, write mode, and type of burst (sequential or linear). the net effect is to achieve performance approaching sram. sdram is rated by operating frequency rather than access time. currently, sdrams are available in 66-mhz, 83-mhz, and 100-mhz speeds. sdram memory does not toggle cas# to get new data, but simply increments a counter to supply the address for succeeding cycles, thus substantially reducing bus delays. the basic characteristics of sdram are as follows: ? the clock is enabled when either ras# or cas# is first sampled asserted. ? the output drivers remain on when cas# is negated. they are turned off when wex# or cs# goes high. ? read data is valid until the next rising clock edge. ? write data is sampled on each rising clock edge. ? dqm[7:0]# determine which bytes are read or written. ? control signals need only be valid during cs#. the bios configures the memory controller for sdram memory operation for each bank of memory by programming offset 60.
5-26 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information figure 5-12 shows an sdram burst read, followed by a single read to address g, then a read access to address x in the other bank. the bank change is indicated by ma11 changing from low to high. figure 5-12. sdram burst read cycle 12345 12345 abc abcd g addr for data a addr for data g addr for data x x bank change dx hclk ads# brdy# w/r# ken# na# ha[31:3] be[7:0]# hd[63:0] md[63:0] sras[c:a]# scas[c:a]# wex# dqm[7:0] ma11 ma10 ma[9:0] cs0# cs1# g
functional operation 5-27 21090c/0june 1997 AMD-640 system controller data sheet preliminary information figure 5-13 shows an sdram burst write, followed by a single write to address g, then a write access to address j in the other bank. the bank change is indicated by ma11 changing from low to high. figure 5-13. sdram write cycle 12345 12345 abc abcd g addr for data a addr for data g addr for data x x bank change dx hclk ads# brdy# w/r# ken# na# ha[31:3] be[7:0] hd[63:0] md[63:0] sras[c:a]# scas[c:a]# wex# dqm[7:0]# ma11 ma10 ma[9:0] cs0# cs1# g
5-28 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information figure 5-14 shows a cpu read miss. as the processor reads data from dram, the cache controller captures the data and stores it in the l2 cache, updating the tag to reflect a new line. note the first gwe# is wider, allowing data a and b to be written sequentially. figure 5-14. cpu read miss a bc d a bc d addr a addr b addr d addr c 13 2 467 5 8 hclk w/r# ads# na# brdy ha[31:3] be[7:0] cadv# cads# ce1# gwe# bwe# coe# tagwe# ta[9:0] ma[9:0] ras[5:0]# cas[7:0]# wex# hd[63:0] md[63:0] cache#
functional operation 5-29 21090c/0june 1997 AMD-640 system controller data sheet preliminary information figure 5-15 shows a read miss with a modified l2 cache line, which must be written back. during the initial read, the cache data (i, j, k, l) is written into the dram write buffer. next, the processor reads data from the dram (a, b, c, d). the cache controller captures the data as it passes to the processor and writes it in the l2 cache, updating the tag to reflect the new line. finally, the data in the write buffer (g, h, i, j) is written to dram. figure 5-15. read miss with modified l2 cache line addr for data a abcd cache write a 135 4 211 22 cache write d read row a col a row g 1 miss gi hj ghij col g addr for data x hclk w/r# ads# na# brdy# ha[31:3] be[7:0]# cadv# cads# ce1# gwe# bwe# coe# tagwe# ta[9:0] ma[9:0] ras[5:0]# cas[5:0] wex# hd[63:0] md[63:0] 23
5-30 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 5.4 pci bus controller the AMD-640 system controller drives the 32-bit pci bus synchronously with the pci clock (pclk), which is a buffered processor clock (hclk) divided by two. it converts 64-bit processor data to 32-bit pci data and regenerates commands with minimum overhead. a five-doubleword cpu-to-pci post write buffer enables the processor and pci to operate concurrently. the AMD-640 system controller converts consecutive processor addresses to burst pci cycles, employing byte merging for optimal cpu-to-pci throughput. its unique integration of pci controller and dram controller functions on one chip provides a fast 32-bit data link, crucial in achieving zero-wait state buffer movement and sophisticated, upgradeable buffer management schemes such as byte merging. a 48-doubleword pci-to-dram post write buffer and a 26-doubleword dram-to-pci prefetch buffer enable concurrent pci bus and dram/cache accesses during pci initiator transactions. 2-1-1-1 cache hit and 3-1-1-1 cache miss timing provide a typical pci bus initiator transfer rate of greater than 100 mbytes per second. when the processor drives an i/o cycle to an address other than the AMD-640 system controllers configuration register addresses, the controller passes the i/o cycle to the pci bus. the AMD-640 system controller posts the i/o cycle in one of its write buffers. the controller does not respond to i/o cycles driven by pci initiators on the pci bus. it allows these cycles to complete on the pci bus. transactions on the pci bus consist of an address/control phase followed by one or more data phases. three signals provide fundamental control of all pci data transfers. frame# is asserted by the initiator to indicate the beginning and end of a transaction. irdy# is asserted by the initiator to indicate that it is ready to complete the current data phase. trdy# is asserted by the target to indicate that it is ready to complete the current data phase. when frame# and irdy# are both inactive, the pci bus is idle. a transaction begins with an address phase, in which an initiator simultaneously asserts frame# and issues the address and bus command. the first data phase begins on the
functional operation 5-31 21090c/0june 1997 AMD-640 system controller data sheet preliminary information following clock edge. data is transferred between the initiator and target on each clock edge for which both irdy# and trdy# are asserted. either the initiator or target can insert wait states by delaying the assertion of irdy# or trdy#, respectively. 5.4.1 pci-to-cpu (read) transactions the AMD-640 system controller contains an eight-byte read buffer which assembles two 32-bit pci read cycles into one 64- bit quadword for the cpu data bus. the buffers are also used when any read crosses a 32-bit boundary. aligned byte/word/dword processor reads are passed on to the pci bus by the AMD-640 system controller as such. the read buffer is always enabled. when the processor reads from the pci bus, the AMD-640 system controller acts as a pci initiator. the controller responds to the read with data from one of its internal buffers or with data obtained by performing a read operation on the pci bus. figure 5-16 depicts a pci read initiated by the AMD-640 system controller. on the first pclk of the read transaction the controller initiates the address phase by asserting frame#, driving the pci bus command on be[3:0]#, and driving the address on ad[31:0]. (frame# remains asserted until either the data phase for the last transaction begins or the cycle is preempted. figure 5-16 depicts a single- transfer read, so frame# is only asserted for one pclk.) on the second pclk, the controller releases ad[31:0] in what is known as the turnaround phase, in which ownership of ad[31:0] changes from the initiator to the target device. the AMD-640 system controller also begins driving the byte enables on be[3:0]# during the second pclk to indicate which data paths will be used for the transfer, and asserts irdy# to indicate it is ready to accept data. during the third pclk, the target device asserts devsel# to indicate that its address matches the one driven for the cycle and that it is ready to begin returning data. in addition to devsel#, the target device drives the requested data on ad[31:0] and asserts trdy# to indicate the data is available. on the rising edge of the fourth pclk, the AMD-640 system controller samples irdy#, trdy#, and ad[31:0]. since irdy# and trdy# are both sampled active, the system controller accepts the data on ad[31:0]. the controller either forwards this data on to the
5-32 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information processor or stores it in one of its read buffers. if the target device needs to insert wait states before returning data, it does so by delaying the assertion of trdy#. figure 5-16. basic pci read operation figure 5-17 depicts a pci burst read, which requires four data transfers, initiated by the AMD-640 system controller. in this example, the target inserts a wait state before the fourth data transfer by deasserting trdy# for one pclk and then reasserting trdy# when it is ready to supply the data for the fourth transfer. figure 5-17. pci burst read operation 12345 addr data1 cmd be# address phase data phase idle clk frame# ad c/be# irdy# trdy# devsel 1234 567 8 9 addr data1 data2 cmd data3 be# address phase data phase data phase data phase idle clk frame# ad c/be# irdy# trdy# devsel data4
functional operation 5-33 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 5.4.2 cpu-to-pci (write) transactions the AMD-640 system controller converts a full 64-bit (quadword) cpu-to-pci write into two consecutive 32-bit (doubleword) pci write cycles. it also features byte merging (grouping smaller, consecutive cpu writes into doublewords) and burst transactions (writing up to four doublewords in a single pci transaction). these features in combination significantly reduce the bus bandwidth required to complete pci writes. the AMD-640 system controller contains a five-doubleword post write buffer between the processor and the pci bus. every cpu-to-pci write is stored in the buffer unless it is full, allowing the processor to begin its next operation without having to wait for the write to complete. when the pci bus is available, the AMD-640 system controller performs up to five 32-bit pci writes to complete the transaction. byte merging byte merging combines multiple cpu write cycles into a single pci transfer. the AMD-640 system controller monitors address and byte enable signals to combine consecutive cycles containing 1, 2, and 4-byte writes into a single 8-byte buffer. the AMD-640 system controller does not allow non-contiguous byte merging. to merge bytes, the second write must be to a subsequent byte location in the 8 byte line. for example, if the first write is a byte write to byte location 3, only subsequent writes to byte locations 4-7 can be merged. if a write is made to locations 0-2, it will be posted to the next write buffer. in addition, the AMD-640 system controller does not allow re- ordering or over-writing merges. this is necessary to maintain support for strong write ordering, in which writes are placed on the pci bus in the order they are received from the processor. the AMD-640 system controller also supports byte merging for writes to the video/frame buffer area. burst cycles the AMD-640 system controller writes all of its buffer contents in a single pci transaction when the bus becomes available. in this way, consecutive cpu-to-pci writes, whether two full quadwords or several smaller transactions combined through byte merging, are performed in a single pci transaction.
5-34 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information writes to pci when the processor writes to the pci bus, the AMD-640 system controller acts as a pci initiator. figure 5-18 depicts a write to pci initiated by the AMD-640 system controller. the controller drives frame#, ad[31:0], and be[3:0]# to initiate the write transaction during the first pclk. frame# remains asserted until the data phase for the last transaction begins or the cycle is preempted. (figure 5-18 depicts a single transfer write, so frame# is only asserted for one pclk.) ad[31:0] contains the address for the target of the write and be[3:0]# contain the bus command (transaction type) information. during the second pclk, the AMD-640 system controller begins driving the data for the write on ad[31:0] and the corresponding byte enables on be[3:0]#. there is no need for a turnaround phase because the controller drives ad[31:0] during both the address and data phases. also during the second pclk, the AMD-640 system controller asserts irdy# to indicate it is driving the data and is ready to complete the transaction. in this example the target is able to decode the address and drive devsel# in the second clock to indicate that its address matches the one driven for the cycle, and it drives trdy# to indicate it is ready to accept data. on the rising edge of the third pclk, the target samples irdy#, trdy#, and ad[31:0]. because both irdy# and trdy# are sampled active, the target accepts the data written on ad[31:0]. this is a zero- wait state write transaction. in most cases, the target device will require additional time to decode the address and complete the write. in this case, the target delays the assertion of devsel#. if the target requires additional time to accept the data and complete the write, it delays the assertion of trdy# as well.
functional operation 5-35 21090c/0june 1997 AMD-640 system controller data sheet preliminary information figure 5-18. pci write figure 5-19 depicts a burst write with four data transfers on the pci bus initiated by the AMD-640 system controller. this example also includes a wait state inserted by the target for both the first and the third data transfers. the target inserts the wait state by delaying the assertion of trdy# for the first transfer. to insert a wait state in the third transfer, the target deasserts trdy# for one pclk, then reasserts trdy# when it is ready to receive the third data transfer. figure 5-19. pci burst write 1 2 addr data1 cmd be# address phase data phase idle clk frame# ad c/be# irdy# trdy# devsel 3 12345678 addr data1 data2 cmd data3 be# address phase data data phase idle data4 clk frame# ad c/be# irdy# trdy# devsel phase
5-36 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 5.4.3 pci arbitration the AMD-640 system controller contains the arbitration logic that allocates ownership of the pci bus among itself, the amd-645 peripheral bus controller, and four other pci initiators. for added flexibility, the AMD-640 system controller allows system designers to select several arbitration mechanisms. two mechanisms are controlled by bit 7 in offset 75h (see page 7-39). these mechanisms can be disabled and replaced by four other choices in offset 76h (page 7-40). the adjustments include setting priority weight of the processor over other pci arbiters, selecting req# or frame# as the trigger for new arbitration, and selecting the bus timeout period. the pci bus arbiter implements resource locking, which is selected via configuration register offset 73h, bit 1 (page 7-37). when there are no requests for the bus, ownership defaults to the processor via the AMD-640 system controller. parking the bus in this way is sometimes referred to as cpu-centric arbitration. 5.4.4 pci configuration the AMD-640 system controller uses pci configuration mechanism #1 to select all of the options available for interaction with the processor, dram, l2 cache, and the pci bus. this mechanism is defined in the pci local bus specification revision 2.1 and described on page 7-1. all configuration functions for the AMD-640 system controller are performed via two i/o-mapped configuration registers, io_cntrl (i/o address 0cf8h) and io_data (i/o address 0cfch). these two registers are used to access all other internal configuration registers of the AMD-640 system controller. the AMD-640 system controller decodes accesses to these two i/o addresses and handles them internally. a read to a non- existent configuration register returns a value of ffh. accesses to all other i/o addresses are forwarded to the pci bus as regular i/o cycles.
functional operation 5-37 21090c/0june 1997 AMD-640 system controller data sheet preliminary information read and write cycles involving the AMD-640 system controller configuration registers are functionally the same as other i/o read and write cycles. both require five pci clock cycles to complete. configuration timing is illustrated in figure 5-20 and figure 5-21. figure 5-20. configuration write figure 5-21. configuration read a addr a write 123456 8 79 12 hclk ads# be[7:0]# na# ha[31:3] brdy# w/r# hd[63:0] pclk 345 a 12345 addr a addr e 12345 6 hclk ads# be[7:0]# na# ha[31:3] brdy# w/r3 hd[63:0] pclk
5-38 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 5.4.5 pci transaction examples cpu read from pci target figure 5-22 shows the processor reading from a target on the pci bus. there is a six-clock latency from the pci bus to the cpu bus. the single wait state on the pci bus is included as an example and is not required. figure 5-22. processor read from pci target iord be[3:0]# addr data a data a data b data b addr iord 13 246 5 hclk w/r# ads# brdy# ha[31:3] be[7:0]# hd[63:0] pclk frame# devsel# ad[31:0] c/be[3:0]# irdy# trdy#
functional operation 5-39 21090c/0june 1997 AMD-640 system controller data sheet preliminary information cpu write to pci target figure 5-23 shows the processor writing to a target on the pci bus. the AMD-640 system controller stores the processor data in the pci write buffer and controls the transfer from the write buffer to the pci bus. there is a seven-clock latency from the processor to the pci bus. the pci write buffer allows the processor to run fast back-to- back cycles. note that na# must be enabled by setting the cpu-to-pci post write bit in the pci buffer control register, offset 70h, bit 7 (see page 7-32). also, back-to-back cycles must be enabled in the command register, offset 05h, bit 9 (see page 7-6). figure 5-23. processor write to pci target ab cd abc iowr addr addr addr addr d 13 246 57 hclk w/r# ads# na# brdy# ha31-ha3 be[7:0]# hd63-hd0 pclk frame# devsel ad31-ad0 c/be[3:0]# irdy# trdy#
5-40 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information pci bus initiator read: cache miss figure 5-24 shows a pci bus initiator reading from memory. a page miss is indicated by ras# toggling high, then low, to strobe in the new page address. the page miss accounts for the latency shown. note that an entire cache line (a, b, c, d, e, f, g, h) is read from dram even though only four 32-bit words (a, b, c, d) are requested (frame# is negated at c). also note that the dram data is echoed on the processor bus, indicating that there is no concurrence during this transfer. the numbers on the clocks are for reference, i.e., there are 3 clocks from ras# to cas#, 5 clocks from ras# to data, and 11 pclks from frame# to the first data word on the pci bus in this example.
functional operation 5-41 21090c/0june 1997 AMD-640 system controller data sheet preliminary information figure 5-24. pci bus initiator read: cache miss snoop ab cd ef gh 12345 1 6 123 abcd row a col a begin memory read ab cd ef gh 7891011 miss addr mrd 45 hclk w/r# ads# eads# brdy ha[31:3] be[7:0]# hitm# ahold boff# hd[63:0] md[63:0] ma[13:0] ras[5:0]# cas[7:0]# wex# pclk frame# devsel# ad[31:0] c/be[3:0]# irdy# trdy# req# gnt# 23
5-42 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information pci bus initiator read: modified l1 hit, l2 miss figure 5-25 shows a pci initiator read. l1 and l2 are snooped for the data. l2 misses, but l1 hits a modified line (indicated by hitm#). the l1 cache controller writes the data to the dram write buffer and the pci read buffer via the pci forward mechanism. the pci initiator reads the data from the pci read buffer while the dram controller writes the data to dram. the l2 cache is not updated because the line is not present in l2.
functional operation 5-43 21090c/0june 1997 AMD-640 system controller data sheet preliminary information figure 5-25. pci bus initiator read: modified l1 hit, l2 miss snoop l1 ab cd gh ef ab ef gh modified data from cache data to dram acd data forwarded to pci snoop l2 l1 hit addr mrd hclk w/r# ads# eads# brdy# ha[31:3] be[7:0]# hitm# ahold boff# cads# coe# hd[63:0] md[63:0] ma[13:0] ras[5:0]# cas[7:0]# wex# pclk frame# devsel# ad[31:0] c/be[3:0]# irdy# trdy# req# gnt# cd b
5-44 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information pci bus initiator read: l1 miss, unmodified l2 hit figure 5-26 shows a pci initiator read. l1 and l2 are snooped. l1 misses but l2 hits. there is no write to dram because the line is not modified. the l2 cache data is forwarded to the pci bus. note that the entire cache line is read, and if a successive pci read addresses this data, it will be supplied directly from the AMD-640 system controller. figure 5-26. pci bus initiator read: l1 miss, unmodified l2 hit snoop l1 l2 enabled ac bd snoop l2 hit not modified a note read ahead mrd addr be[3:0]# hclk w/r# ads# eads# brdy# ha[31:3] be[7:0]# hitm# ahold boff# cadv# cads# coe# ce1# tagwe# ta[9:0] hd[63:0] pclk frame# devsel# ad[31:0] c/be[3:0]# irdy# trdy# req# gnt#
functional operation 5-45 21090c/0june 1997 AMD-640 system controller data sheet preliminary information pci bus initiator read: modified l1 hit figure 5-27 shows another pci initiator read. l1 and l2 are snooped. l1 has a hit on a modified line (hitm# is asserted). l2 also has a hit. the l1 data is written to both the l2 cache and the pci read buffer. figure 5-27. pci bus initiator read: modified l1 hit snoop l1 l2 miss write l1 data to l2 ab cd gh ef b c d addr mrd be[3:0]# hit modified hclk w/r# ads# eads# brdy# ha[31:3] be[7:0]# hitm # ahold boff# cadv# cads# coe# gwe# bwe# ce1# tagwe# ta[9:0] hd[63:0] pclk frame# devsel ad[31:0] c/be[3:0]# irdy# trdy# req# gnt# a
5-46 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information pci bus initiator write: cache miss figure 5-28 shows a pci write to dram. l1 and l2 are snooped, and both miss. the AMD-640 system controller stores the pci data into its write buffer and subsequently writes this data (a, b, c, d) to dram. figure 5-28. pci bus initiator write: cache miss addr mwr be[3:0]# abcd data written to dram write buffer snoop l1 miss snoop l2 miss begin dram write a,b c,d 123456 78 910 12 11 13 hclk w/r# ads# eads # brdy# ha31-ha3 be[7:0]# cads# coe# hitm# ahold boff# hd63-hd0 md63-md0 ma13-ma0 ras[5:0]# cas[7:0]# wex# pclk frame# devsel# ad31-ad0 c/be[3:0]# irdy# trdy# req# gnt#
functional operation 5-47 21090c/0june 1997 AMD-640 system controller data sheet preliminary information pci bus initiator write: l1 hit, l2 miss figure 5-29 shows a pci write to dram. l1 and l2 are snooped. l2 is a miss and l1 is a hit. the l1 cache controller writes data (g, h, i, j, k, l, m, n) to the dram write buffer. this data is merged with the data from the pci bus (a, b, c, d) and written into dram. the cache line boundaries are assumed. there are many possible variations to the example shown. figure 5-29. pci bus initiator write: l1 hit, l2 miss addr mwr be[3:0]# abcd snoop l1 hit snoop l2 miss gh ij mn kl merged data written to dram ab lm cd jk cpu write to dram buffer hclk w/r# ads# eads# brdy# ha[31:3] be[7:0]# cads# coe# hitm# ahold boff# hd[63:0] md[63:0] ma[13:0] ras[5:0]# cas[7:0]# wex# pclk frame# devsel# ad[31:0] c/be[3:0]# irdy# trdy#
5-48 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information pci bus initiator write: l1 miss, unmodified l2 hit figure 5-30 shows a pci write to dram. l1 and l2 are snooped. l1 is a miss and l2 is a hit. the l2 line is not written back because it is not modified. the line is simply marked invalid because new data is written into the dram. figure 5-30. pci bus initiator write: l1 miss, unmodified l2 hit addr mwr acd write to dram buffer snoop l1 hit l2 snoop l2 a,b c,d write to dram mark line invalid hclk w/r# ads# eads# brdy# ha[31:3] be[7:0]# coe# cads# ken#/inv cache# hitm# boff# tagwe# ta[9:0] hd[63:0] md[63:0] ma[13:0] ras[5:0]# cas[7:0]# wex# pclk frame# devsel# ad[31:0] c/be[3:0]# irdy# trdy# b ahold
functional operation 5-49 21090c/0june 1997 AMD-640 system controller data sheet preliminary information pci bus initiator write: modified l1 hit, l2 hit figure 5-31 shows a pci initiator write to dram. l1 and l2 are snooped. the processor asserts hitm# indicating that the line in the l1 cache is modified. l2 also indicates a hit. the l1 data is written back to the dram buffer. the controller then merges the cache data with the pci data and writes the merged data to dram. figure 5-31. pci bus initiator write: modified l1 hit, l2 hit snoop l1 l1 hit modified addr mwr abcd gh j i ab cd j i write l1 data to l2 snoop l2 hit hclk w/r# ads# eads# brdy# ha[31:3] be[7:0]# coe# cads# cache# ken#/inv hitm# ahold boff# tagwe# ta[9:0] hd[63:0] md[63:0] ma[13:0] ras[5:0]# cas[7:0]# wex# pclk frame# devsel# ad[31:0] c/be[3:0]# irdy# trdy#
5-50 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information pci bus initiator write: l1 miss, modified l2 hit figure 5-32 shows a pci initiator write to dram. l1 and l2 are snooped. l1 is a miss but l2 is a hit and is modified. the controller reads the modified l2 line into the dram write buffer, merges it with the pci data, and writes the merged data to dram. tagwe# invalidates the l2 cache entry by writing ffh. the first cas# assertion indicates that a dram read access is started in parallel with interrogating the cache. the dram read aborts when the write cache hit is recognized. figure 5-32. pci bus initiator write: l1 miss, modified l2 hit snoop l1 addr mwr abcd write to dram gij h read data from l2 ab i cd j snoop l2 hit ff invalidate l2 entry read started hclk w/r3 ads# eads# brdy# ha[31:3] be[7:0]# ken#/inv cache# hitm# ahold boff# cadv# coe# cads# ce1# gwe# tagwe# ta[9:0] hd[63:0] md[63:0] ma[13:0] ras[5:0]# cas[7:0] wex# pclk frame# devsel# ad[31:0] c/be[3:0]# irdy# trdy#
functional operation 5-51 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 5.4.6 pci accesses by another initiator a pci initiator begins a memory read or write cycle by asserting frame# and placing the memory address on ad[31:0]. the AMD-640 system controller decodes the address. if the address is within the domain of the host or memory, the AMD-640 system controller accepts the cycle and responds as a pci target by asserting devsel#. (if the address is not within controller or processor domain, the AMD-640 system controller ignores the cycle and allows it to complete on pci.) pci reads in a pci read, the AMD-640 system controller combines the 16- doubleword pci buffer with the 10-doubleword dram read buffer, effectively forming a 26-doubleword pci read buffer. the controller initiates a memory prefetch starting at the address sent by the initiator, reading data sequentially until the pci read buffer is full. when the first doubleword of data is available, the controller supplies the data on ad[31:0] and asserts trdy#, as shown in figure 5-27 on page 5-45. as space becomes available, more data is prefetched until the cycle is complete. when the entire read is completed, the buffers are automatically invalidated to prevent stale data from being put out on a subsequent pci initiator read. if a read operation crosses a memory page boundary, the AMD-640 system controller initiates a target disconnect on the pci bus at a line (32-byte) boundary. each address is passed to the processor bus to snoop the primary and secondary caches. if the address hits a cache entry, the data is supplied from the cache rather than from dram. to maintain data coherency, the AMD-640 system controller completes pci initiator writes to memory before starting a pci read. pci writes in a pci write, the AMD-640 system controller combines the 16-doubleword pci buffer with the 32-doubleword dram write buffer, effectively forming a 48-doubleword pci write buffer. the AMD-640 system controller asserts trdy# during the same clock it asserts devsel#. on the next rising clock edge the controller samples the write data and posts it in the pci write buffer, as shown in figure 5-28 on page 5-46. posting the write frees the pci bus so that the next operation is not stalled waiting for completion of the write to memory.
5-52 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information if the buffer fills up before the write is complete, the controller will deassert trdy# until the buffer has written some of its contents to memory and space is available for more data. the write is completed when the memory bus becomes available. the l1 and l2 caches are snooped during the write to maintain cache integrity. if the address hits a cache entry the cache data is written and merged with the pci data. the cache line is also invalidated. to maintain data coherency, the write buffer snoops pci reads from memory. if read data hits the write buffer, the read stalls by negating trdy# until the write is completed. 5.4.7 pci fast back to back cycles the pci specification allows fast back-to-back cycles to the same target or to different targets. in the AMD-640 system controller, this feature is controlled by the command register (offset 05hC04h) for reads and the pci configuration register (offset 71h), bit 7 for writes. offset 73h, bit 7 must be set for slow decode if fast back-to-back is selected. on same-target back-to-back cycles, the initiator is responsible for preventing contention on trdy#, devsel#, stop#, and perr#. the AMD-640 system controller deletes the idle cycle prior to frame# and guarantees it will not produce any contention when it is driving the pci bus. on different-target back-to-back cycles, the target is responsible for preventing contention on trdy#, devsel#, stop#, and perr#. when this option is selected the AMD-640 system controller will capture the address without an intervening idle cycle. the AMD-640 system controller will delay assertion of trdy#, devsel#, stop#, and perr# by one clock to avoid contention. avoiding contention in this mode is more difficult because the capabilities of all targets in the system must be known.
functional operation 5-53 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 5.4.8 pci sideband signals the AMD-640 system controller supports one pair of pci sideband signals, preq# and pack#, to connect to a bridge device such as an isa/eisa bridge. they are generally used when an alternate bus device, typically an isa master or dma device, requires ownership of the systems main memory. the alternate bus device asserts preq# to request the bus. the AMD-640 system controller grants the request after all of its write buffers have been flushed by asserting pack#. 5.4.9 power management the AMD-640 system controller supports the advanced power management specification, version 2.1. the counters required for this feature are contained in the amd-645 peripheral bus controller companion device. smiact controls selection of the smm memory space. to initialize the smm memory, the bios writes 01 to offset 63h, bits 1-0. this enables it to copy the smm code into the smm memory. the bios then writes 00, then 10 to these bits. (the program should not change the bits from 01 to 10 directly.) this action enables the controller to redirect processor accesses to the appropriate address range if smiact# is active. to avoid cache coherence problems in smm mode, connect the smiact# signal to flush# on the processor.
5-54 functional operation AMD-640 system controller data sheet 21090c/0june 1997 preliminary information
initialization 6-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 6 initialization all programmable features in the AMD-640 system controller are controlled by the pci configuration registers, which are normally written to only during system initialization. this section summarizes the register functions, default values, access types, and addresses (offset numbers). for more detailed descriptions of the configuration registers, see section 7. recommended values are shown for fpm, edo, and sdram. these values ensure acceptable performance but may not be optimal for a particular system. refer to the bios guide for sample code. access types are indicated as follows: r/w read/write r/o read only rwc read, write 1s to clear individual bits table 6-1. configuration space header registers offset pci header default access 01hC00h vendor id 1106h ro 03hC02h device id 0595h ro 05hC04h command 0007h rw 07hC06h status 02a0h rwc 08h revision id nn (note 1) ro 09h program interface 00h ro 0ah bus class code 00h ro 0bh base class code 06h ro 0ch cache line size 00h ro 0dh latency timer 00h rw 0eh header type 00h ro 0fh built-in self test (bist) 00h ro 10hC3fh reserved 00h note: 1. nn changes for each device revision. rev d = 02h is the current revision as of publication of this document (rev e = 03h, rev f = 04h).
6-2 initialization AMD-640 system controller data sheet 21090c/0june 1997 preliminary information table 6-2. configuration space cache control registers offset cache control default recommended access setting result 50h cache control 1 00h 83h normal operation, pbsram rw 51h cache control 2 00h 01h 1 bank; 512 kbytes rw 52h non-cacheable control 02h 96h l1=l2=wb rw 53h system performance control 00h 78h pci concurrency rw 55hC54h non-cacheable region #1 0000h rw 57C56h non-cacheable region #2 0000h rw
initialization 6-3 21090c/0june 1997 AMD-640 system controller data sheet preliminary information table 6-3. configuration space dram control registers offset cache control default recommended access setting result 58h dram configuration register #1 40h 44h 10-bit column rw 59h dram configuration register #2 05h 03h banks 0-3 populated rw 5ah dram bank 0 ending [ha29-22] 01h 10h/02h 64mbytes/8mbytes rw 5bh dram bank 1 ending [ha29-22] 01h 20h/04h 64mbytes/8mbytes rw 5c dram bank 2 ending [ha29-22] 01h 30h/06h 64mbytes/8mbytes rw 5dh dram bank 3 ending [ha29-22] 01h 40h/08h 64mbytes/8mbytes rw 5eh dram bank 4 ending [ha29-22] 01h 50h/08h 64mbytes/no ram rw 5fh dram bank 5 ending [ha29-22] 01h 60h/08h 64mbytes/no ram rw 60h dram type 00h 00h 05h fast page mode edo mode banks 0-3 rw 61h shadow ram control register #1 00h cah video bios rw 62h shadow ram control register #2 00h 00h disable rw 63h shadow ram control register #3 00h 22h main bios rw 64h dram timing abh ffh 44h 57h slowest initially 60 ns edo 60 ns fp rw 65h dram control register #1 00h a8h page open fast decode latch delay rw 66h dram control register #2 00h 01h sdram rw 67h 32-bit dram width control register 00h 00h 64-bit dram rw 69hC68h reserved 6ah dram refresh counter 00h 42h 15 m sec rw 6bh dram refresh control register 00h 80h cbr rw 6ch sdram control register 00h 00h rw 6dh dram drive strength control register 00h 4fh 24-ma drive rw 6eh ecc control register 00h 00h rw 6fh ecc status register 00h 00h rwc
6-4 initialization AMD-640 system controller data sheet 21090c/0june 1997 preliminary information table 6-4. configuration space pci control registers offset cache control default recommended access setting result 70h pci buffer control 1 00h e0h enable write buffers & prefetch rw 71h processor to pci flow control #1 00h deh post writes to dram & merge rw 72h processor to pci flow control #2 02h ech reduce frame rwc 73h pci target control 00h 8dh stop control rw 74h pci initiator control 00h c0h enhance commands rw 75h pci arbitration control #1 00h 00h 76h pci arbitration control #2 00h 80h rw
configuration registers 7-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 7 configuration registers all of the many options available on the AMD-640 system controller are selected by writing to its configuration registers. these registers are usually set during system initialization and are not accessed during normal operation. however, some registers may require specific programming sequences during power-up to detect the type and size of installed memory. this section contains a description of the mechanism used to access the AMD-640 system controllers configuration registers and describes the location and definition of each register. 7.1 pci configuration mechanism the AMD-640 system controller uses pci configuration mechanism #1 to convey and receive configuration data to and from the host processor. this mechanism, described in pci local bus specification revision 2.1 , employs i/o locations 0cf8hC0cfbh to specify the target address and locations 0cfchC0cffh for data to or from the target address. the target address includes the pci bus, device, function, and register numbers of the pci device. to specify the AMD-640 system controller, set bit 31, the enable bit. if bit 31 is cleared, the AMD-640 system controller passes the data through as an i/o transaction. the bus number, device number, and function number of the AMD-640 system controller are all 00h. note: in the AMD-640 system controller, idsel is internally connected to ad11. other pci devices in a system must connect their idsel lines to a unique line in ad[31:12], and cannot use ad11. configuration address ports 0cfbhC0cf8h 31 bit 30 C bit 24 bit 23 C bit 16 bit 15 C bit 11 10 C 8 bit 7 C bit 2 1 0 en reserved bus number device number function # register number 0 0 i/o address ocfbh i/o address ocfah i/o address ocf9h i/o address ocf8h
7-2 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information the pci specification calls for 256 configuration registers in each target device to be organized on doubleword boundaries. each register is numbered as an offset from zero. to access a particular register, the most significant six bits of the offset are written to bits 7-2 of the target address to specify the registers doubleword boundary, while the pci byte enable lines c/be[3:0]# select the byte represented by the least two significant bits of the offset. some registers are described as 16- or 32-bit entities, in which case two or four byte enable lines, respectively, are asserted. for example, the status register is described as residing at offset 07hC06h. 07h = 00000111b and 06h = 00000110b. to access this register, write the six most significant bits (000001 in this example) of either byte to bits 7 2 of i/o address 0cf8h to specify the doubleword (all multi-byte registers reside within the same doubleword), and assert byte enables 3 and 2 (clear c/be3# and c/be2#) corresponding to the two least significant bits of 07h and 06h, respectively. table 7-1 summarizes the i/o ports involved in pci configuration. table 7-1. configuration port register summary register name i/o address type default value size io_cntrl 0cf8h r/w 0000 0000h 32 io_data32 0cfch r/w 0000 0000h 32 io_odd_data16 0cfch r/w 0000h 16 io_even_data16 0cfeh r/w 0000h 16 io_0_data8 0cfch r/w 00h 8 io_1_data8 0cfdh r/w 00h 8 io_2_data8 0cfeh r/w 00h 8 io_3_data8 0cffh r/w 00h 8
configuration registers 7-3 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 7.2 register overview tables 7-2 through 7-5 summarize the AMD-640 system controller configuration register offsets, functions, default values, and access types. access types are indicated as follows: r/w read/write r/o read only rwc read, write 1s to clear individual bits notes: 1. nn changes for each device revision. rev d = 02h was the current revision as of publication of this document (rev e = 03h, rev f = 04h). table 7-2. configuration space header registers offset pci header default access 01hC00h vendor id 1106h ro 03hC02h device id 1595h ro 05hC04h command 0007h rw 07hC06h status 02a0h rwc 08h revision id nn (note 1) ro 09h program interface 00h ro 0ah bus class code 00h ro 0bh base class code 06h ro 0ch cache line size 00h ro 0dh latency timer 00h rw 0eh header type 00h ro 0fh built-in self test (bist) 00h ro 10hC3fh reserved 00h table 7-3. configuration space cache control registers offset cache control default access 50h cache control 1 00h rw 51h cache control 2 00h rw 52h non-cacheable control 02h rw 53h system performance control 00h rw 55hC54h non-cacheable region #1 0000h rw 57hC56h non-cacheable region #2 0000h rw
7-4 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information table 7-4. configuration space dram control registers offset cache control default access 58h dram configuration register #1 40h rw 59h dram configuration register #2 05h rw 5ah dram bank 0 ending 01h rw 5bh dram bank 1 ending 01h rw 5ch dram bank 2 ending 01h rw 5dh dram bank 3 ending 01h rw 5eh dram bank 4 ending 01h rw 5fh dram bank 5 ending 01h rw 60h dram type 00h rw 61h shadow ram control register #1 00h rw 62h shadow ram control register #2 00h rw 63h shadow ram control register #3 00h rw 64h dram timing abh rw 65h dram control register #1 00h rw 66h dram control register #2 00h rw 67h 32-bit dram width control register 00h rw 68h reserved 00h rw 69h reserved 00h rw 6ah dram refresh counter 00h rw 6bh dram refresh control register 00h rw 6ch sdram control register 00h rw 6dh dram drive strength control register 00h rw 6eh ecc control register 00h rw 6fh ecc status register 00h rwc
configuration registers 7-5 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 7.3 pci configuration space registers this read-only value is defined as 1106h. this read-only value of 1595h represents the AMD-640 system controller. table 7-5. configuration space pci control registers offset pci bus control default access 70h pci buffer control register 00h rw 71h processor-to-pci control register#1 00h rw 72h processor-to-pci control register#2 00h rwc 73h pci initiator control register #1 00h rw 74h pci initiator control register #2 00h rw 75h pci arbitration control register #1 00h rw 76h pci arbitration control register #2 00h rw 77hCffh reserved 00h rw 7. 3 .1 vendor id (offset 01hC00h) bit 1514131211109 8 7654321bit 0 vendor id reset0001000100000110 7.3.2 device id (offset 03hC02h) bit 1514131211109 8 7654321bit 0 device id reset0001010110010101
7-6 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bits 15C10 reserved (always reads 0) bit 9 fast back-to-back cycle enable (rw) see section 5.4.7 on page 5-52 for a discussion of back-to-back cycles. 0 =fast back-to-back transactions only allowed to the same agent (default) 1 = fast back-to-back transactions allowed to different agents bit 8 serr# enable (rw) this bit does not affect setting of bit 14 in offset 07hC 06h. 0 = serr# driver disabled (default) 1 = serr# driver enabled note: if a system error occurs, serr# may be asserted by a pci master or by the amd-645 peripheral bus controller. bit 7 address/data stepping (always reads 0) 0 = device never does stepping bit 6 reserved (rw) this bit must remain at the default value of 0. bit 5 vga palette snoop (always reads 0) 0 = palette accesses generate normal pci cycles bit 4 memory write and invalidate command (always reads 1) this feature increases overall performance by eliminating cache writebacks when a pci initiator writes to the address of a modified line. the AMD-640 system controller invalidates the cache line rather than writing it back to dram. 1 = bus initiators may generate memory write and invalidate bit 3 special cycle monitoring (always reads 0) 0 = special cycles not monitored bit 2 initiator enable (always reads 1) 1 = AMD-640 system controller can behave as bus initiator bit 1 memory space (always reads 1) 1 = responds to memory space bit 0 i/o space (always reads 1) 1 = responds to i/o space 7. 3 . 3 command (offset 05hC04h) bits 15C10 9 8 7654321bit 0 reserved fbbce serre step reserved vgaps mwic scmon initen memspc iospc reset 0 0000010111
configuration registers 7-7 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bit 15 reserved (always reads 0) bit 14 signaled system error (always reads 0) 0=no error detected 1 = ecc error detected. (ecc errors are reported in this status bit but the serr# pin is not asserted.) bit 13 signaled initiator abort (ro) this bit is set by a pci initiator when its transaction is terminated with initiator abort. 0 = pci transactions proceeding normally 1 = the AMD-640 system controller, acting as pci initiator, has terminated a transaction before completion bit 12 received target abort (rwc) the target issues a target abort when it detects a fatal error or cannot complete a transaction. this bit is set by simultaneously deasserting devsel# and asserting stop#. 0=no abort received 1 = transaction aborted by target bit 11 signaled target abort (ro) this bit is set when a pci initiator accesses dram and the AMD-640 system controller cannot respond, or when the AMD-640 system controller accesses a target device and the target cannot respond. 0 = pci transactions proceeding normally 1 = transaction aborted by target bits 10C9 devsel# timing (always reads 01) this field indicates that the slowest devsel# timing will be medium. 00 = fast 01 = medium (AMD-640 system controller only implements this timing) 10 = slow 11 = reserved bit 8 data parity error detected (ro) the AMD-640 system controller samples the pci par line to check for parity errors during a pci read. 0=no parity error 1 = parity error was detected bit 7 fast back-to-back capable (always reads 1) the AMD-640 system controller can accept fast back-to-back transactions, including those from different agents. 7. 3 . 4 status (offset 07hC06h) bit 15 14 13 12 11 10C9 8 7 6 5 bits 4C0 rsvd sse sia rta sta devsel# timing dped fbbc reserved 66 mhz reserved reset 0 0 0 0 0 0 1 0 1 0 1 00000
7-8 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bit 6 user-defined features (always reads 0) the AMD-640 system controller does not support user-defined features . bit 5 66 mhz capable pci bus (always reads 1) the maximum pci bus operating speed is 66 mhz. 4C0 reserved (always reads 0) bits 7C0 AMD-640 system controller revision code (ro) 04h = revision f (as of june 1997). 05h = revision g. 06h = revision h. bits 7C0 AMD-640 system controller programming interface (always reads 00h) this register is defined in different ways for each combination of base and subclass codes. it is undefined for this type of device. 7.3.5 revision id (offset 08h) bit 7654321bit 0 AMD-640 system controller chip revision code reset 7.3.6 programming interface (offset 09h) bit 7654321bit 0 programming interface reset00000000
configuration registers 7-9 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bits 7C0 sub class code (always reads 00h) the pci-defined sub class code for a host bridge is 00h. bits 7C0 base class code (always reads 06h) the pci-defined base class code for a bridge device is 06h. bits 7C0 cache line size (always reads 0) the AMD-640 system controller accepts, but does not implement, the pci memory write and invalidate (mwi) command, for which the cache lines size is a required component. 7.3.7 sub class code (offset 0ah) bit 7654321bit 0 sub class code reset00000000 7.3.8 base class code (offset 0bh) bit 7654321bit 0 base class code reset00000110 7.3.9 cache line size (offset 0ch) bit 7654321bit 0 cache line size reset00000000
7-10 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bits 7C3 latency timer value (rw) this five-bit binary value specifies the latency timer in units of 8 pci bus clocks. 00000 = 32 x 8 pci clocks 00001C11111 = (5-bit binary value) x 8 pci clocks bits 2C0 reserved (always reads 0) bits 7C0 pci header type (ro) the AMD-640 system controller pci header type is 00h. bits 7C0 built-in self test functions (ro) the AMD-640 system controller does not support built-in self-test functions, so this read-only register is 00h. 7.3.10 latency timer (offset 0dh) bit 7654321bit 0 latency timer values reserved reset00000000 7.3.11 header type (offset 0eh) bit 7654321bit 0 header type reset00000000 7.3.12 built-in self test (bist) (offset 0fh) bit 7654321bit 0 built-in self test functions reset00000000
configuration registers 7-11 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 7.4 cache control registers bits 7C6 cache enable (rw) 00 = cache disabled (default) 01 = cache initializationbios fills the l2 cache to a known state 10 = cache enablednormal operation 11 = reserved bit 5 reserved (rw) this bit must remain at the default value 1. bits 4C3 tag configuration (rw) 00 = 8+08 tag bits, no modify bit (default) 01 = 7+17 tag bits, one modify bit 10 = 10+010 tag bits, no modify bit 11 = 9+19 tag bits, one modify bit bit 2 reserved (always reads 0) bits 1C0 cache sram type (rw) 00 = no sram (default) 01 = reserved 10 = burst sram 11 = pipeline burst sram 7.4.1 cache control register 1 (offset 50h) bit 7654321bit 0 cachen reserved tagcon reserved srmtyp reset00100000
7-12 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bits 7C6 reserved (always reads 0) bit 5 backoff processor (rw) used when register 52h, bit 2 is set for l2 fill when cache# is inactive. this bit should normally be cleared to 0 for best performance, although system-level performance differences are usually negligible. 0 =defer ready return (i.e., do not assert brdy#) until l2 is filled (default) 1 = backoff processor (assert boff#) until l2 is filled bit 4 reserved (always reads 0) bit 3 sram banks (rw) 0 = one bank (default). with no na# delay, pipelined read hit timing is 3- 1-1-1-1-1-1-1 (no bank to switch). 1 = two banks. with no na# delay, pipelined read hit timing is 3-1-1-1-2-1- 1-1 for bank switch. bit 2 reserved (always reads 0) bits 1C0 total l2 cache size 00 = 256 kbytes (default) 01 = 512 kbytes 10 = 1 mbyte 11 = 2 mbytes 7.4.2 cache control register 2 (offset 51h) bit 7654321bit 0 reserved bop reserved srambnk reserved cache size reset00000000
configuration registers 7-13 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bit 7 l2 write-protect / l2 cacheability for addresses c0000hCc7fffh (rw) bit 6 l2 write-protect / l2 cacheability for addresses d0000hCdffffh (rw) bit 5 l2 write-protect / l2 cacheability for addresses e0000hCeffffh (rw) bit 4 l2 write-protect / l2 cacheability for addresses f0000hC fffffh (rw) each of these bits enables its associated l2 cache address range to contain the associated bios code, which can improve performance. setting these bits not only enables bios caching but protects the cached bios from modification by inadvertent writes. when one of these bits is set, a read access in the associated address range will load data into the cache, and subsequent reads will come from the cache. a write will not affect the l2 cache contents but will be passed to dram. (refer to registers 61hC63h on page 7-28 for dram response to writes.) 0 = address range is neither cacheable nor write-protected (default) 1 = address range is both cacheable and write-protected. bit 3 reserved (always reads 0) bit 2 l2 fill (rw) setting this bit forces the requested data to be filled into the l2 cache (provided that l2 cache is enabled), even if the processor does a read cycle with cache# deasserted. although the AMD-640 system controller ignores the non-cacheable settings in the processor when this bit is set, it still adheres to the non-cacheable settings in its configuration registers. 0 = normal l2 cache fill (default) 1 = force l2 cache fill note: setting this bit significantly improves performance. bit 1 reserved (rw) 1= (default) bit 0 l2 writeback or writethrough (rw) this bit determines if the l2 cache operates as writeback or writethrough. 0 = writeback (default) 1 = writethrough 7.4.3 non-cacheable control register (offset 52h) bit 7654321bit 0 wpc wpd wpe wpf reserved l2fill reserved l2wbwt reset00000010
7-14 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bit 7 read-around-write (rw) this feature gives read priority over write. if data is queued in the write buffer, a read request will be serviced before the write is completed. when read-around-write is disabled, read and write requests are serviced in the order they are received. 0 = disable (default) 1 = enable (offset 65h, bit 0 must also be set) bit 6 cache read pipeline cycle (rw) bit 5 cache write pipeline cycle (rw) bit 4 dram pipeline cycle (rw) each of these bits enables the corresponding pipeline cycles when set. also, na# is asserted during pipelined cycles, but not otherwise. 0 = disable (default) 1 = enable bit 3 pci initiator peer concurrence (rw) 0 = disabled (default). the arbiter will assign the memory to the pci port. 1 = enabled. a pci initiator can transfer data to a target pci device without tying up the memory or cpu buses. bits 2C0 reserved (always reads 0) 7.4.4 system performance control register (offset 53h) bit 7654321bit 0 raw crpc cwpc dpc pcimpc reserved reset00000000
configuration registers 7-15 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bits 15C11,7C0 base address (rw) bits 15C11 and bits 7C0 determine the base address of the non-cacheable region. the default value of these bits is zero, specifying the lowest 64 kbytes of the address range. bits 10C8 address range r2Cr0 (rw) bits 10C8 specify the size of the cache area to be non-cacheable, starting from the base address. note that the non- cacheable region must be "region aligned". for example a 128-kbyte range must be on aligned on a 128 kbyte boundary, a 1-mbyte range on a 1- mbyte boundary, etc. 000 = disabled (default) 001 = 64 kbytes 010 = 128 kbytes 011 = 256 kbytes 100 = 512 kbytes 101 = 1 mbyte 110 = 2 mbytes 111 = 4 mbytes 7. 4 . 5 non-cacheable region #1 (offset 55hC54h) bit 1514131211109 8 7654321bit 0 a20 a19 a18 a17 a16 r2 r1 r0 a28 a27 a26 a25 a24 a23 a22 a21 reset0000000000000000 7.4.6 non-cacheable region #2 (offset 57hC56h) bit 1514131211109 8 7654321bit 0 a20 a19 a18 a17 a16 r2 r1 r0 a28 a27 a26 a25 a24 a23 a22 a21 reset0000000000000000
7-16 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 7.5 dram control registers bits 7C5 memory address map type for banks 0 and 1 (rw) edo/fp dram 000 = 8-bit column address 001 = 9-bit column address 010 = 10-bit column address (default) 011 = 11-bit column address 100 = 12-bit column address 101 to 111 = reserved sdram 0xx = 16-mbit sdram (default) 1xx = 64-mbit sdram bit 4 reserved (always reads 0) bits 3C1 memory address map type for banks 2 and 3 (rw) edo/fp dram 000 = 8-bit column address (default) 001 = 9-bit column address 010 = 10-bit column address 011 = 11-bit column address 100 = 12-bit column address 101 to 111 = reserved sdram 0xx = 16-mbit sdram (default) 1xx = 64-mbit sdram bit 0 reserved (always reads 0) 7.5.1 dram configuration register #1 (offset 58h) bit 7654321bit 0 memory address map type for banks 0C1 reserved memory address map type for banks 2C3 reserved reset01000000
configuration registers 7-17 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bits 7C5 memory address map type for banks 4 and 5 (rw) edo/fpm dram 000 = 8-bit column address (default) 001 = 9-bit column address 010 = 10-bit column address 011 = 11-bit column address 100 = 12-bit column address 101 to 111 = reserved sdram 0xx = 16-mbit sdram (default) 1xx = 64-mbit sdram table 7-6 on page 7-18 shows how the host address bus lines map to memory address bus lines for several dram configurations. note that ma11 selects the bank for 2-bank sdrams and ma13 selects the bank for 4-bank sdrams. pc will be zero on page hits and 1 on page misses. pc is also 1 if offset 6c selects the all banks precharge command. this command is normally only used during bios initialization. bits 4C3 reserved (always reads 0) 2C0 last dram bank populated (rw) 000 = bank 0 001 = bank 1 010 = bank 2 011 = bank 3 100 = bank 4 101 = bank 5 (default) 110 to 111 = reserved note: the cacheable properties of a memory address vary with its bank number, as follows: n bank 0, bank 1 and bank 5 are cacheable. n bank 2, bank 3 and bank 4 are non-cacheable if tag = 10 + modified bit. n bank 2, bank 3 and bank 4 are cacheable if tag is any other configuration than 10 + modify bit. 7.5.2 dram configuration register #2 (offset 59h) bit 7654321bit 0 memory address map type for banks 4C5 reserved last dram bank populated reset00000000
7-18 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information table 7-6. mapping host address lines to memory address lines edo/fp dram reg 59h bits 7 C5 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 row:col 000 row column 23 22 21 11 20 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 12:8, 13:8 001 row column 24 23 22 21 20 11 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 10:9, 12:9, 13:9 010 row column 25 24 23 21 22 20 11 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 11:10, 12:10, 13:10 011 row column 26 25 23 24 21 22 20 11 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 12:11, 13:11 100 row column 27 25 26 23 24 21 22 20 11 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 13:12 sdram reg 59h bits 7C5 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 row:col 0xx 16 mbit row column 11 11 22 pc 21 24 20 23 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 11:10, 11:9, 11:8 1xx 64 mbit rev c row column 12 12 13 13 25 11 22 pc 21 26 20 11 19 10 18 9 17 8 16 7 15 6 14 5 24 4 23 3 x4 (14:10) x8 (14:9) 1xx 64 mbit rev d row column 25 25 12 12 13 13 22 pc 21 26 20 11 19 10 18 9 17 8 16 7 15 6 14 5 24 4 23 3 x4 (14:10) x8 (14:9)
configuration registers 7-19 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bits 7C0 dram bank ending address bits 29C22 (rw) these registers are used to steer ras#/cas# lines to the correct memory banks. each of these registers defaults to 01h. table 7-7 illustrates several examples. 7.5.3 dram bank 0 ending address (offset 5ah) dram bank 1 ending address (offset 5bh) dram bank 2 ending address (offset 5ch) dram bank 3 ending address (offset 5dh) dram bank 4 ending address (offset 5eh) dram bank 5 ending address (offset 5fh) bit 7654321bit 0 ha29 ha28 ha27 ha26 ha25 ha24 ha23 ha22 reset00000001 table 7-7. ending address register settings memory bank offset example 1 example 2 example 3 memory size register values memory size register values memory size register values bank 0 5ah 4 mbytes 01h 4 mbytes 01h 8 mbytes 02h bank 1 5bh 4 mbytes 02h 8 mbytes 03h 8 mbytes 04h bank 2 5ch 4 mbytes 03h 4 mbytes 04h 16 mbytes 08h bank 3 5dh 03h 04h 08h bank 4 5eh 03h 04h 08h bank 5 5fh 03h 04h 08h notes: 1. the bios must fill the ending address register for each bank whether or not the bank is populated. the endings must be in incre- mental order.
7-20 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bits 7C6 reserved (always reads 0) bits 5C4 dram type for banks 5C4 (rw) bits 3C2 dram type for banks 3C2 (rw) bits 1C0 dram type for banks 1C0 (rw) 00 = fast page mode(fpm) dram (default) 01 = extended data out (edo) dram 10 = reserved 11 = synchronous dram (sdram) 7.5.4 dram type (offset 60h) bit 7654321bit 0 reserved dram type for banks 5C4 dram type for banks 3C2 dram type for banks 1C0 reset00000000
configuration registers 7-21 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bits 7C6 shadow ram control for addresses cc000Ccffffh (rw) bits 5C4 shadow ram control for addresses c8000Ccbfffh (rw) bits 3C2 shadow ram control for addresses c4000Cc7fffh (rw) bits 1C0 shadow ram control for addresses c0000Cc3fffh (rw) bits 7C6 shadow ram control for addresses dc000Cdcffffh (rw) bits 5C4 shadow ram control for addresses d8000Cdbfffh (rw) bits 3C2 shadow ram control for addresses d4000Cd7fffh (rw) bits 1C0 shadow ram control for addresses d0000Cd3fffh (rw) each pair of bits controls the accessibility of its corresponding address range as follows: 00 = shadowing (read and write) disabled (default) 01 = write enabled 10 = read enabled 11 = read and write enabled shadow control registers (offsets 61hC63h) a memory read/write is considered shadowed when the accessed memory segment(s) in lower memory are intercepted by the AMD-640 system controller and redirected to data copies in the upper memory area. each 16-kbyte segment in the uma (64- kbyte segments in addresses e0000hCfffffh) can be enabled for shadowing by setting at least one of its corresponding two bits in offsets 61hC63h. shadowing can be enabled for read only, write only, or both. 7.5.5 shadow ram control register #1 (offset 61h) bit 7654321bit 0 cc000Ccffffh c8000Ccbfffh c4000Cc7fffh c0000Cc3fffh reset00000000 7.5.6 shadow ram control register #2 (offset 62h) bit 7654321bit 0 dc000Cdffffh d8000Cdbfffh d4000Cd7fffh d0000Cd3fffh reset00000000
7-22 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bits 7C6 shadow ram control for addresses e0000Ce ffffh (rw) bits 5C4 shadow ram control for addresses f0000C fffffh (rw) each pair of bits controls the accessibility of its corresponding address range as follows: 00 = shadowing (read and write) disabled (default) 01 = write enabled 10 = read enabled 11 = read and write enabled bits 3C2 memory hole (rw) 00 = none (default) 01 = 512 kbytes - 640 kbytes (80000Cbffffh) 10 = 15 mbytes - 16 mbytes (f0000Cfffffh) 11 = 14 mbytes - 16 mbytes (e0000Cfffffh) note: the memory hole is used on certain legacy isa boards and is generally not used in pci systems. bit 1 smi redirect (rw) setting this bit redirects ram accesses from graphics memory to other areas of system memory as follows: 30000hC3ffffh is redirected to b0000hCbffffh. 40000hC4ffffh is redirected to a0000hCaffffh. 0 = disable redirection (default) 1 = enable redirection. bit 0 access to dram addresses a0000Cb ffffh (rw) addresses a0000hCbffffh are reserved for use by vga controllers for system access to the vga frame buffer. setting this bit directs accesses in this range to the corresponding memory addresses in system dram rather than to the pci bus for vga frame buffer access. this feature is used to initialize b0000hC bffffh for smm mode. 0 = disable read and write to a0000hCbffffh (default) 1 = enable read and write to a0000hCbffffh note: smiact# should be connected to the processor flush# signal to avoid cache coherency problems in smm mode. 7.5.7 shadow ram control register #3 (offset 63h) bit 7654321bit 0 e0000Ceffffh f0000Cfffffh memory hole smi redirect vga dram reset00000000
configuration registers 7-23 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bits 7-6 ras# precharge time (rw) 00 = 2t (50 ns dram) 01 = 3t (60 ns dram) 10 = 4t (70 ns dram) (default) 11 = 6t bits 5-4 ras# pulse width (rw) 00 = 3t (50 ns dram) 01 = 4t (60 ns dram) 10 = 5t (70 ns dram) (default) 11 = 6t bits 3-2 cas# pulse width (rw) these two bits determine the number of cas cycles for fast page mode and edo dram, as shown in table 7-8. bit 1 write pulse width (rw) 0=1t 1 = 2t (default) bit 0 column address to cas# delay (rw) 0=1t 1 = 2t (default) note: t = 1 hclk period. 7.5.8 dram timing (offset 64h) bit 7654321bit 0 ras# precharge time ras# pulse width cas# pulse width write pw cacas#d reset10101011 table 7-8. cas# pulse width bits 3C2 fpm cycles edo cycles 00 1t 4t 01 2t 1t 10 3t 2t 11 4t 3t
7-24 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bits 7C6 page mode control (rw) 00 = page closes after access (default) 01 = reserved 10 = page stays open after access until page time out or page miss 11 = page closes if processor is idle, i.e., there has been no dram access for 8 cpu cycles bit 5 fast dram decoding enable (rw) this bit should be enabled to reduce dram leadoff time. the timings in the diagrams presented in section 5 refer to operations with this bit set. 0 = disable fast dram decoding (default) 1 = enable fast dram decoding bit 4 edo dram leadoff cycle reduction (rw) set this bit only if system bus is 50 mhz or slower. bit 4 has no effect unless bit 5 is set. 0 = normal edo dram leadoff cycle (default) (normal leadoff is 6t) 1 = reduce edo dram leadoff cycle by 1t bit 3 dram data latch delay (rw) systems that use ecc can set this bit to increase data setup time. 0 = latch dram data normally (default) 1 = delay dram data latch by 1/2 clock bits 2C1 reserved (always reads 0) bit 0 dram read cycle delay (rw) this bit must be set if read-around-write is enabled (offset 53h, bit 7). 0 = no delay (default) 1 = delay dram read cycle 1t when write buffer is not empty note: t = 1 hclk period. 7.5.9 dram control register #1 (offset 65h) bit 7654321bit 0 page mode control fdde edlcr ddld reserved drcd reset00000000
configuration registers 7-25 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bit 7 edo test mode enable (rw) this bit is enabled by the bios to detect if the dram is fpm or edo. the controller delays brdy# for 15 sec after cas# goes high. if the dram is fpm, the data on the bus will discharge during this time and read incorrectly. if it is edo the data will be valid . 0 = normal mode (default) 1 = edo test mode bits 6C3 reserved (always reads 0) bit 2 memory data to host data fifo control (rw) this bit is set only if a layout problem exists on the processor bus. 0 = 0 wait states for memory data-to-host data pop (default) 1 = 1 wait state for memory data-to-host data pop bit 1 sdram ras# precharge reduction (rw) this bit is only set for sdram. it has no effect if sdram is not selected in offset 60h. 0 = normal ras# precharge (set by bits 6 and 7 in register 64h) (default) 1 = reduce ras# precharge 1t for sdram bit 0 sdram ras#-to-cas# delay reduction (rw) this bit is only set for sdram. it has no effect if sdram is not selected in offset 60h. 0 = normal ras#-to-cas# delay (2t) (default) 1 = reduce ras# (active) to cas# (command) delay for sdram note: t = 1 hclk period. 7.5.10 dram control register #2 (offset 66h) bit 7654321bit 0 edotme reserved mhfc srpr srcdr reset00000000
7-26 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bit 7 ras#-to-column address delay (rw) 0 = 1t (default) 1=2t bit 6 na# delay (rw) 0 = no na# delay (default). 1= delay na# 1t. the timing for a read hit depends on both the na# delay and the number of pbsram banks, indicated by offset 51h, bit 3 (page 7-12) as shown in table 7-9. bit 5 bank 5 width (rw) bit 4 bank 4 width (rw) bit 3 bank 3 width (rw) bit 2 bank 2 width (rw) bit 1 bank 1 width (rw) bit 0 bank 0 width (rw) these bits should all be cleared. note: t = 1 hclk period. 7.5.11 32-bit dram width control register (offset 67h) bit 7654321bit 0 rcad na delay bank 5 width bank 4 width bank 3 width bank 2 width bank 1 width bank 0 width reset00000000 table 7-9. pbsram timing offset 67h bit 6 offset 51h bit 3 pbsram read hit timing 0 0 3-1-1-1-1-1-1-1 0 1 3-1-1-1-2-1-1-1 1 0 3-1-1-1-2-1-1-1 1 1 3-1-1-1-3-1-1-1
configuration registers 7-27 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bits 7C0 refresh counter (rw) this 8-bit binary number represents the number of time units between dram refresh cycles. each time unit equals 16 processor clocks. the default value is zero. at 66 mhz, 16 clocks = 240 ns. for example, to set the refresh interval to 15.625 m sec, set this register to (15.625 m sec/240 ns) = 65 decimal = 41 hex. note: when this register is set to zero, dram refresh is disabled. bit 7 cas#-before-ras# refresh (rw) 0 = disabled (default) (ras#-only refresh) 1 = enabled bit 6 burst refresh (rw) 0 = disable burst refresh (1 row refreshed every 15 sec) (default) 1 = enable burst refresh (4 rows refreshed every 60 sec) bits 5C0 reserved (always reads 0) 7.5.12 dram refresh counter (offset 6ah) bit 7654321bit 0 refresh counter reset00000000 7.5.13 dram refresh control register (offset 6bh) bit 7654321bit 0 cbr refresh burst refresh reserved reset00000000
7-28 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bit 7 64 mbit sdram interleave (rw) this bit is relevant only for 64-mbit sdram with bit 5 set. 0 = 2-bank interleave (default) 1 = 4-bank interleave bit 6 sdram burst write (rw) 0 = disabled (default) 1 = enabled bit 5 sdram bank interleave enable (rw) this feature increases performance by reducing the number of clocks required. 0 = disabled (default). timing for a 3-line burst is 8-1-1-1-3-1-1-1-3-1-1-1. 1 = enabled. timing for a 3-line burst is 8-1-1-1-1-1-1-1-1-1-1-1. bit 4 reserved (always reads 0) bit 3 sdram cas# latency (rw) 0 = cycle latency is 2 (default) 1 = cycle latency is 3 note: it is possible to program cas latencies of 1, 2, or 3 into any sdram bank regardless of the value set by bit 3. programming a different cas latency value in memory than the value implemented by this register can result in miscommunication. bits 2C0 sdram operation mode select (rw) these commands are used in the sdram detection algorithm. refer to the bios porting guide. 000 = normal sdram mode (default) 001 = nop command enabled 010 = cpu-to-dram cycles are converted to all banks precharge commands 011 = cpu-to-dram cycles are converted to commands driven on ma[11:0]. the bios selects an appropriate host address for each memory row of memory to generate the appropriate commands. 100 = cas#-before-ras# cycle enable 101 to 111 = reserved 7.5.14 sdram control register (offset 6ch) bit 7654321bit 0 64mbsi sbw sbie reserved scl soms reset00000000
configuration registers 7-29 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bit 7 bank decoding test (rw) 0 = normal operation (default) 1 = for production test only. do not set. bit 6 ma[1:0] drive (rw) 0 = 12 ma (default) 1=24 ma bit 5 ma[1:0]/ras[5:4]# (rw) this pin determines whether pins n17 and m17 function as ras[5:4]# or secondary drivers for ma[1:0] as shown in table 7-10. bit 4 force smm mode (rw) when this bit is set the AMD-640 system controller responds as if the smiact# pin was asserted. 0 = smm mode not forced (default) 1 = smm mode forced. bit 3 sdram command drive (sras#, scas#, wex#) (rw) 0 = 12 ma (default) 1=24 ma bit 2 ma[13:2] and wex# drive (rw) 0 = 12 ma (default) 1=24 ma bit 1 cas# drive (rw) 0 = 12 ma (default) 1=24 ma bit 0 ras# drive (rw) 0 = 12 ma (default) 1=24 ma 7.5.15 dram drive strength control register (offset 6dh) bit 7654321bit 0 bdt ma[1:0] drive ma/ras# force smm sdramcd ma&wed cas# drive ras# drive reset00000000 table 7-10. functions of pins n17 and m17 bit 5 pin n17 function pin m17 function drive control 0 ras5# ras4# reg. 6dh, bit 0 1 ma1 ma0 reg. 6dh, bit 6
7-30 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bit 7 ecc/normal mode select (rw) 0 = parity (default) 1 = ecc bit 6 reserved (always reads 0) bit 5 enable serr# on ecc (multi-bit) error (rw) 0= dont assert serr# for ecc errors (default) 1 = assert serr# for ecc errors bit 4 enable serr# on ecc (single-bit) error (rw) 0 = do not assert serr# for ecc errors (default) 1 = assert serr# for ecc errors bit 3 ecc cycle timing for cpu-sdram reads (rw) 0 = normal cpu sdram reads (default) 1 = add 1t for cpu sdram read cycles with ecc. the extra cycle is required if ecc mode is enabled. bit 2 ecc enable bank 5/4 (rw) bit 1 ecc enable bank 3/2 (rw) bit 0 ecc enable bank 1/0 (rw) 0 = disabled (default) 1 = enabled 7.5.16 ecc control register (offset 6eh) bit 7654321bit 0 enms reserved esee esee ectpdr eee5/4 ee3/2 eee1/0 reset00000000
configuration registers 7-31 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bit 7 multi-bit error detected (rwc) write 1 to this bit to clear it. bits 6C4 multi-bit error dram bank (rwc) these bits contain the encoded value of the dram bank containing the multi-bit error. write 1s to these bits to clear them. 000 = bank 1 (default) 001 = bank 2 010 = bank 3 011 = bank 4 100 = bank 5 101 = bank 6 bit 3 single-bit ecc error (rwc) write 1 to this bit to clear it. single bit errors are corrected but not written back to memory. bits 2C0 single-bit error dram bank (rwc) these bits contain the encoded value of the dram bank containing the single-bit error. write 1s to these bits to clear them. 000 = bank 1 (default) 001 = bank 2 010 = bank 3 011 = bank 4 100 = bank 5 101 = bank 6 7.5.17 ecc status register (offset 6fh) bit 7654321bit 0 mbed multi-bit error dram bank sbe single-bit error dram bank reset00000000
7-32 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 7.6 pci bus control registers bit 7 cpu-to-pci post-write (rwc) 0 = disabled (default) 1 = enabled bit 6 pci initiator-to-dram post-write (rw) 0 = disabled (default) 1 = enabled bit 5 pci initiator-to-dram prefetch (rw) 0 = disabled (default) 1 = enabled bits 4C2 reserved (always reads 0) bit 1 pci retry for processor qw (quadword) access (rw) by default, the controller backs off the processor if the second doubleword of a pci access is delayed, and starts over with the first dword, potentially resulting in a system deadlock. clearing bit 1 avoids this hazard by preventing the controller from asserting boff# during the second dword access. this feature should always be enabled. 0 = enabled (recommended) 1 = disabled (default) bit 0 disable flush of cpu-to-pci buffer (rw) by default, the AMD-640 system controller writes all contents in the pci write buffer (i.e., flushes the buffer) before granting the bus to another pci initiator. this feature allows the AMD-640 system controller to grant the pci bus to another initiator before the write buffer is emptied. enabling this feature reduces grant latency. 0 = flushing cpu-to-pci buffer has priority (default) 1 = grant to another pci initiator has priority 7.6.1 pci buffer control register (offset 70h) bit 7654321bit 0 cppw pidpw pidp reserved prpqwa noflush reset00000000
configuration registers 7-33 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bits 7 & 3 pci burst control bits (rw) these two bits determine how the AMD-640 system controller processes cpu-to-pci write transactions, as shown in table 7-11. bit 6 byte merge (rw) setting this bit enables the AMD-640 system controller to collect bytes and write them as a word or doubleword. 0 = disabled (default) 1 = enabled bit 5 reserved (always reads 1) bit 4 pci i/o cycle post write (rw) enabling this feature allows the cpu to proceed after posting a pci write. this is the preferred setting. if this feature is disabled, the processor is held in a wait state until the pci write is completed. 0 = disabled (default) 1 = enabled bit 2 enable pci fast back-to-back write (rw) see section 5.4.7 on page 5-52 for a discussion of fast back-to-back reads. 0 = disabled (default) 1 = enabled (generates na#) 7.6.2 processor-to-pci flow control register #1 (offset 71h) bit 7654321bit 0 burst2 byte merge reserved piocpw burst1 epfbbw eqfg e1wspc reset00100000 table 7-11. pci burst control bits bit 7 bit 3 operation 0 0 every write transaction goes to the write buffer. no burst operations occur. this is the default setting. 0 1 burst writes are placed in the write buffer. burst operations are later performed on the pci bus. non-burst writes are immediately written to the pci bus after the write buffers are flushed. 1 x every write transaction is placed in the write buffer. burst operations are performed on burstable transactions. regular pci writes are performed on non-burstable transactions. this is the setting for normal operation.
7-34 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bit 1 enable quick frame generation (rw) when this bit is set, frame# is generated one pci clock earlier than in standard pci operation. this is the recommended setting. 0 = disabled (default) 1 = enabled (recommended) bit 0 enable 1-wait-state pci cycles (rw) the AMD-640 system controller delays assertion of irdy# one clock cycle when this bit is set. 0 = disabled (default) 1 = enabled
configuration registers 7-35 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bit 7 retry status (rwc) this bit indicates that a cpu-to-pci transaction has been retried unsuccessfully either 16 or 64 times (see bits 5C4). write a 1 to this bit position to clear the bit. 0 = no retry has occurred (default) 1 = retry has occurred bit 6 retry timeout action (rw) 0 = retry continuously and record status only (default) 1 = flush buffer and return ffffffffh for read bits 5C4 retry count and retry backoff (rw) 00 = retry two times and backoff processor (default) 01 = retry 16 times and set retry status (bit 7) 10 = retry 4 times and backoff processor 11 = retry 64 times and set retry status (bit 7) bit 3 clear failed data and continue retry (rw) the post write buffer stores data going from the cpu to the pci bus. if the target is not ready to accept the data a retry will occur. if the cycle fails to complete after the number of retry attempts specified in bits 5C4, the data will be discarded (popped) if bit 3 is set. this makes room in the post write buffer to accept new data from the processor. 0 = disable (default) 1 = flush (pop) the failed data and continue posting when posting retries fail bit 2 processor backoff on pci read retry failure (rw) this feature generates boff# when a pci read retry fails, momentarily boosting priority of the pci. 0 = disabled (default) 1 = enabled bit 1 reduce 1t for frame# generation (rw) when this bit is set, frame# is generated one pci clock earlier than the setting in register 71h, bit 1. doing so may cause timing problems and is not recommended. 0 = disabled (default) (recommended) 1 = enabled 7.6.3 processor-to-pci flow control register #2 (offset 72h) bit 7654321bit 0 retry status rta retry count and backoff cfdcr pbprrf r1tfg r1tprpt reset00000000
7-36 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bit 0 reduce 1t for processor read of pci target (rw) setting this bit reduces the delay from trdy# to brdy# by one hclk to speed up system performance. 0 = disabled (default) 1 = enabled
configuration registers 7-37 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bit 7 local memory decoding (rw) this bit must be set if fast back-to-back cycles are selected in either register 04h-05h or register 71h . 0 = fast (address phase) (default) 1 = slow (first data phase) bit 6 pci target 1 wait state read (rw) 0 = zero wait state trdy# response (default) 1 = one wait state trdy# response bit 5 pci target 1 wait state write (rw) 0 = zero wait state trdy# response (default) 1 = one wait state trdy# response bit 4 reserved (always reads 0) bit 3 assert stop# after write timeout (rw) enabling this feature allows the AMD-640 system controller to signal a retry to the initiator by asserting stop#. this is the recommended setting. 0 = disabled (default) 1 = enabled (recommended) bit 2 assert stop# after read timeout (rw)) enabling this feature allows the AMD-640 system controller to signal a retry to the initiator by asserting stop#. this is the recommended setting. 0 = disabled (default) 1 = enabled (recommended) bit 1 lock# function (rw) when this bit is enabled, the AMD-640 system controller samples the lock# pin on the pci bus and reserves the resource per the pci specification. the controller does not assert lock# during cpu- to-pci cycles. 0 = disabled (default) 1 = enabled 7.6.4 pci target control register (offset 73h) bit 7654321bit 0 lmd pt1wsw pt1wsr reserved asawt asart lock pibte reset00000000
7-38 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bit 0 pci initiator broken timer enable (rw) setting this bit forces the AMD-640 system controller to initiate pci arbitration in the event that frame# has not been asserted 16 pci clocks after the last gnt# was issued. 0 = disabled (default) 1 = enabled bit 7 pci enhanced command support (rw) setting this bit improves performance by enabling the memory read line (mrl), memory read multiple (mrm), and memory write and invalidated (mwi) pci commands. mrl and mrm make dram access more efficient by enabling burst accesses to the dram. mwi prevents unnecessary snoops on the processor bus. 0 = disabled (default) 1 = enabled bit 6 pci initiator single write merge (rw) enabling this function reduces pci bus traffic to improve bus utilization. this is accomplished by collecting bytes or words and forming them into one doubleword. for example, if the processor performs four consecutive byte writes, they will be combined into one 32-bit transfer on the pci bus. 0 = disabled (default) 1 = enabled bits 5C0 reserved (always reads 0) 7.6.5 pci initiator control register (offset 74h) bit 7654321bit 0 pecs piswm reserved reset00000000
configuration registers 7-39 21090c/0june 1997 AMD-640 system controller data sheet preliminary information bit 7 arbitration priority (rw) setting bit 7 forces fair arbitration between pci initiators and the processor employing round-robin (rotating) arbitration. by default, the prioity order is fixed as follows: 1. req1# 2. req2# 3. req3# 4. req4# 5. preq# 6. cpu 0 = fixed priority (default) 1 = fair arbitration note: if register 76h bit 7 is set, the processor has higher priority than the pci bus, and its operation overrides the priority selected by register 75h bit 7. bit 6 arbitration mode (rw) 0 = req#-based (arbitrate at end of req#) (default) 1 = frame#-based (arbitrate at end of each frame#). this enables a higher priority initiator to preempt a lower priority initiator. bits 5C4 reserved (always reads 0) bits 3C0 pci initiator bus timeout (rw) bits 3C0 represent the binary number of idle time periods the AMD-640 system controller allows on the pci bus before forcing arbitration. each time period is equal to 32 pci clock cycles. the default value of 0000h disables this feature. 7.6.6 pci arbitration control register #1 (offset 75h) bit 7654321bit 0 arbpri arbmode reserved pci initiator bus time-out reset00000000
7-40 configuration registers AMD-640 system controller data sheet 21090c/0june 1997 preliminary information bit 7 initiator priority rotation enable (rw) 0 = disabled (arbitration per register 75h, bit 7) (default) 1= enabled (arbitration per bits 5C4 below) bit 6 reserved (always reads 0) bits 5C4 initiator priority rotation control (rw) 00 = disabled (arbitration per register 75h bit 7) (default) 01 = grant to processor after every pci initiator grant. the processor is guaranteed access to the pci bus after the current pci initiator completes, regardless of the number or priority of other requesting pci initiators. 10 = grant to processor after every two pci initiator grants. the processor is guaranteed access to the pci bus after the current pci initiator and one more pci initiator complete. 11 = grant to processor after every three pci initiator grants. the processor is guaranteed access to the pci bus after the current pci initiator and two more pci initiators complete. bits 3C0 reserved (always reads 0) 7.6.7 pci arbitration control register #2 (offset 76h) bit 7654321bit 0 ipre reserved iprc reserved reset00000000
electrical data 8-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 8 electrical data 8.1 absolute ratings long-term reliability and functional integrity of the AMD-640 system controller are guaranteed as long as it is not subjected to conditions exceeding the absolute ratings listed in table 8-1. table 8-1. absolute ratings parameter minimum maximum comments v dd -0.5 v 5.5 v core supply v dd3 -0.5 v 3.6 i/o supply v pin (processor) -0.5 v v dd3 +0.5 v or 4.0 v, whichever is lower note 1 v pin (pci and dram) -0.5 v v dd + note 2 t case (under bias) -65 c+110 c t storage -65 c+150 c notes: 1. the voltage on any i/o pin on the cpu interface must not be greater than 0.5 v above the voltage being applied to v dd3 . in addition, the v pin voltage must never exceed 4.0 v 2. the voltage on any i/o pin on the pci or drma interface must not be greater than 0.5 v above the voltage being applied to v dd3
8-2 electrical data AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 8.2 operating ranges the functional operation of the AMD-640 system controller is guaranteed if the voltage and temperature parameters are within the limits defined in table 8-2. table 8-2. operating ranges parameter minimum typical maximum comments v dd 4.75 v 5.0 v 5.25 v core (note 1) v dd3 3.135 v 3.3v 3.6 v i/o (note 1) t case 0 c70 c notes: 1. v dd and v dd3 are referenced from v ss .
electrical data 8-3 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 8.3 dc characteristics table 8-3. dc characteristics symbol parameter description preliminary data comments min max v il input low voltage -0.50 v 0.8 v v ih input high voltage (processor) 2.0 v v dd3 +0.5 v note 1 v ih input high voltage (pci and dram) 2.0 v v dd +0.5 v v ol output low voltage 0.45 v i ol = 4.0-ma load v oh output high voltage 2.4 v i oh = 1.0-ma load i dd 5 v power supply current 0.40 a 66 mhz, note 2 i dd3 3 v power supply current 0.35 a 66 mhz, note 3 i li input leakage current 10 m a note 4 i lo output leakage current 20 m a note 4 i il input leakage current bias with pullup 40 m a note 5 i ih input leakage current bias with pulldown -40 m a note 6 c in input capacitance 10 pf c out output capacitance 15pf c out i/o capacitance 20 pf c clk clk capacitance 10 pf c tin test input capacitance (tdi, tms, trst) 10 pf c tout test output capacitance (tdo) 15 pf c tck tck capacitance 10 pf notes: 1. v dd3 refers to the voltage being applied to v dd3 during functional operation. 2. v dd2 = 5.25 v the maximum power supply current must be taken into account when designing a power supply. 3. v dd3 = 3.6 v the maximum power supply current must be taken into account when designing a power supply. 4. refers to inputs and i/o without an internal pullup resistor and 0 v in v dd3. 5. refers to inputs with an internal pullup and v il = 0.4v. 6. refers to inputs with an internal pulldown and v ih = 2.4v.
8-4 electrical data AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 8.4 power dissipation table 8-4 shows typical and maximum power dissipation of the AMD-640 system controller during normal and reduced power states. the measurements are taken with hclk = 66 mhz, v dd = 5.0 v, and v dd3 = 3.3 v. table 8-4. typical and maximum power dissipation clock control state typical ( note 1) maximum (note 2) comments normal (thermal power) 1.8 w 2.5 w note 3 stop grant /halt 0.21 w note 4 stop clock 0.175 w note 5 notes: 1. typical power is measured during instruction sequences or functions associated with normal system operation. 2. maximum power is determined for the worst-case instruction sequence or function for the listed clock control states. 3. the maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal dissipation for the AMD-640 system controller proces- sor. 4. the clk signal and the internal pll are still running but most internal clocking has stopped. 5. the clk signal, the internal pll, and all internal clocking has stopped.
switching characteristics 9-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 9 switching characteristics the AMD-640 system controller signal switching characteristics are presented in tables 9-1 through 9-7. valid delay, float, setup, and hold timing specifications are listed. all signal timings are based on the following conditions: n the target signals are input or output signals that are switching from logical 0 to 1, or from logical 1 to 0. n measurements are taken from the time the reference signal (hclk, pclk, or reset) passes through 1.5v to the time the target signal passes through 1.5v. n all signal slew rates are 1 v/ns, from 0v to 3v (rising) or 3v to 0v (falling). n parameters are within those listed in operating ranges on page 8-2. n the load capacitance (c l ) on each signal is 0 pf with the exception of maximum timings for clock, processor, dram and cache, where the c l = 50 pf.
9-2 switching characteristics AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 9.1 clk switching characteristics table 9-1 and table 9-2 contain the switching characteristics of the hclk input to the AMD-640 system controller for 66-mhz and 60-mhz cpu bus operation, respectively. table 9-3 contains the switching characteristics of the pclk input for 33-mhz pci bus operation. these timings are all measured with respect to the voltage levels indicated by figure 9-1 on page 9-3. the clk period stability specifies the variance (jitter) allowed between successive periods of the clk input measured at 1.5v. this parameter must be considered as one of the elements of clock skew between the AMD-640 system controller and the system logic. table 9-1. hclk switching characteristics for 66-mhz bus operation symbol parameter description preliminary data figure comments min max frequency 33.3 mhz 66.6 mhz t 2 hclk high time 6.0 ns 9-1 t 3 hclk low time 6.0 ns 9-1 t 4 hclk fall time 0.15 ns 1.5 ns 9-1 t 5 hclk rise time 0.15 ns 1.5 ns 9-1 hclk period stability 250 ps note 1 notes: 1. jitter frequency power spectrum peaking must occur at frequencies greater than (hclk frequency)/3 or less than 500 khz. table 9-2. hclk switching characteristics for 60-mhz bus operation symbol parameter description preliminary data figure comments min max frequency 30 mhz 60 mhz t 2 hclk high time 6.0 ns 9-1 t 3 hclk low time 6.0 ns 9-1 t 4 hclk fall time 0.15 ns 1.5 ns 9-1 notes: 1. jitter frequency power spectrum peaking must occur at frequencies greater than (frequency of clk)/3 or less than 500 khz.
switching characteristics 9-3 21090c/0june 1997 AMD-640 system controller data sheet preliminary information figure 9-1. clk waveform t 5 hclk rise time 0.15 ns 1.5 ns 9-1 hclk period stability 250 ps note 1 table 9-3. pclk switching characteristics for 33-mhz pci bus symbol parameter description preliminary data figure comments min max t1 pclk cycle 30 ns ? t 2 pclk high time 11.0 ns 9-1 t 3 pclk low time 11.0 ns 9-1 t 4 pclk fall time 1 v/ns 4v/ns 9-1 t 5 pclk rise time 1 v/ns 4v/ns 9-1 pclk period stability 250 ps note 1 notes: 1. jitter frequency power spectrum peaking must occur at frequencies greater than (hclk frequency)/3 or less than 500 khz. table 9-2. hclk switching characteristics for 60-mhz bus operation (continued) symbol parameter description preliminary data figure comments min max notes: 1. jitter frequency power spectrum peaking must occur at frequencies greater than (frequency of clk)/3 or less than 500 khz. 0.8 v 1.5 v 2.0 v t 5 t 1 t 4 t 3 t 2
9-4 switching characteristics AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 9.2 valid delay, float, setup, and hold timings the following valid delay and float timings for output signals during functional operation are relative to the rising edge of the given clock. the maximum valid delay timings are provided to allow a system designer to determine if setup times can be met. likewise, the minimum valid delay timings are used to analyze hold times. the setup and hold time requirements for the AMD-640 system controller input signals presented here must be met by any device that interfaces with it to assure the proper operation of the AMD-640 system controller. figure 9-2 illustrates the relationship between the rising clock edge and setup, hold, and valid data timings. figure 9-2. setup, hold, and valid delay timing diagram t su t h t vd t vd data in data out clk
switching characteristics 9-5 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 9.3 processor interface timing all of the following timings are relative to hclk. pads 0 to 13 are driver types. for system simulation, select the pad from the appropriate ibis model. table 9-4. processor cycle timing symbol parameter description preliminary data figure comments min max t su setup time for ads# dc# hlock# cache# smiact# be[7:0]# ha[31:3] 5 ns 9-2 t su w/r# 5.5 ns t su setup time for m/io# hitm# 69-2 t su setup time for hd[63:0] 3 ns 9-2 t h hold time for smiact# hitm# w/r# cache# m/io# be[7:0]# d/c# ha[31:3] 1 ns 9-2 t h ads# hold time 1.5 ns 9-2 t h hlock# hold time 1.0 ns 9-2 t h hd[63:0] hold time 2 ns 9-2 t vd valid delay for ahold boff# ken#/inv eads# 1.5 ns 7 ns 9-2 pad 0 (note 1) brdy#, na# valid delay 1.5 ns 8 ns 9-2 pad 0 (note 1) ha[31:3] valid delay 2 ns 13 ns 9-2 pad 2 (note 1) hd[63:0] valid delay 1.5 ns 8.5 ns 9-2 pad 1 (note 1) t fd ha[31:3] float delay 4 ns 9 ns 9-2 note 1 notes: 1. measurements are taken with no load.
9-6 switching characteristics AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 9.4 pci interface timing all of the following timings are relative to pclk. table 9-5. pci interface timing symbol parameter description preliminary data figure comments min max t su ad[31:0] setup time 7 ns 9-2 preq#, req[3:0]# setup time 12 ns 9-2 setup time for frame# stop# trdy# devsel# irdy# c/be[3:0]# reset# 7 ns 9-2 t h ad[31:0] hold time 0 ns 9-2 hold time for frame# stop# trdy# devsel# irdy# c/be[3:0]# preq# req[3:0]# 0 ns 9-2 t vd ad[31:0] valid delay (address phase) 2 ns 11 ns 9-2 pad 12 (note 1) ad[31:0] valid delay (data phase) 2 ns 11 ns 9-2 pad 12 (note 1) valid delay for frame# stop# trdy# devsel# irdy# c/be[3:0]# gnt[3:0]# 2 ns 11 ns 9-2 pad 13 (note 1) pgnt# valid delay 2 ns 12 ns 9-2 t fd float delay for frame# stop# trdy# devsel# irdy# c/be[3:0]# 28 ns 9-2 (note 1) t pw reset# pulse width 2 clks 9-2 t lat req# to gnt# latency 3 clks 9-2 notes: 1. measurements are taken with no load for t min , 50 pf for t max.
switching characteristics 9-7 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 9.5 dram interface timing all of the following timings are relative to hclk. table 9-6. dram interface timing symbol parameter description preliminary data figure comments min max t su md[63:0] setup (sdram) 2 ns 9-2 md[63:0] setup (edo/fp) 2 ns 9-2 t h md[63:0] hold (sdram) 2.5 ns 9-2 md[63:0] hold (edo/fpm) 4 ns 9-2 t vd ras[5:0]# valid delay (edo) 1.5 ns 8 ns 9-2 pad 5 (note 1) cs[5:0]# valid delay (sdram) 2 ns 8 ns 9-2 pad 5 (note 1) cas[7:0]# valid delay (edo) 1.5 ns 8 ns 9-2 pad 7 (note 1) dqm[7:0]# valid delay (sdram) 2ns 7 ns 9-2 pad 11 (note 1) sras[c:a]# valid delay (sdram) 2 ns 7 ns 9-2 pad 5 (note 1) scas[c:a]# valid delay (sdram) 2 ns 7 ns 9-2 pad 5 (note 1) we[c:a]# valid delay 2 ns 7 ns 9-2 pad 5 (note 1) ma[13:2] valid delay 2 ns 10 ns 9-2 pad 5 (note 1) ma[1:0] valid delay 2 ns 10 ns 9-2 pad 5 (note 1) md[63:0] valid delay (sdram) 2 ns 7 ns 9-2 pad 1 (note 1) md[63:0] valid delay (edo/fpm) 2 ns 12 ns 9-2 pad 1 (note 1) t ft ma[11:0] flow-through delay from ha for first read cycle 2 ns 10 ns 9-2 pad 5 (note 1) notes: 1. measurements are taken with no load.
9-8 switching characteristics AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 9.6 l2 cache timing all of the following timings are relative to hclk. table 9-7. l2 cache timing symbol parameter description preliminary data figure comments min max t su ta9Cta0 setup time 6.7 ns 9-2 t h ta9Cta0 hold time 2 ns 9-2 t vd ta9Cta0 valid delay 2 ns 9 ns 9-2 pad 1 (note 1) valid delay for ce1 cads cadv 1.5ns 7 ns 9-2 pad 0 (note 1) coe, tagwe valid delay 1.5 ns 10 ns pad 0 (note 1) gwe, bwe valid delay 1.5 ns 9 ns pad 0 (note 1) notes: 1. measurements are taken with no load.
ibis models 10-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 10 ibis models all of the AMD-640 system controllers inputs, outputs, and bidirectional buffers are implemented using a 3.3-v buffer design. in addition, a subset of the controllers i/o buffers includes a second, higher drive strength option. these buffers can be configured to provide the higher drive strength for applications that place a heavier load on these i/o signals. amd has developed several i/o buffer models that represent the characteristics of each of the possible drive strength configurations supported by the AMD-640 system controller. amd developed the models to allow system designers to perform analog simulations of AMD-640 system controller signals that interface with the rest of the system. analog simulations are used to determine a signals time of flight from source to destination and to ensure the systems signal quality requirements are met. signal quality measurements include overshoot, undershoot, slope reversal, and ringing. 10.1 selectable drive strength the driver types are specified in the ac table. the model also associates the appropriate driver type to its respective pin. only the memory drivers are programmable by configuration registers. hence the designer must select the 12-ma or-24 ma driver, depending on the intended use.
10-2 ibis models AMD-640 system controller data sheet 21090c/0june 1997 preliminary information 10.2 i/o buffer model amd provides models of the AMD-640 system controller i/o buffers for system designers to use in board-level simulations. these i/o buffer models conform to the i/o buffer information specification (ibis), version 2.1 . each i/o model contains voltage versus current (v/i) and voltage versus time (v/t) data tables to model the of i/o buffer behavior accurately. the following list summarizes the properties of each i/o buffer model: n all data tables contain minimum, typical, and maximum values to allow for worst-case, typical, and best-case simulations, respectively. n the pullup, pulldown, power clamp, and ground clamp device v/i tables contain sufficient data points for accurate representation of the nonlinear nature of the v/i curves. in addition, the voltage ranges provided in these tables extend beyond the normal operating range of the AMD-640 system controller to accommodate simulators that can yield more accurate results based on this wider range. n rising and falling ramp rates are specified. n the min/typ/max v dd3 operating range is specified as 3.135 v, 3.3 v, and 3.465 v, respectively. n v il = 0.8 v, v ih = 2.0 v, and v meas = 1.5 v. n the r/l/c of the package is modeled. n the capacitance of the silicon die is modeled. n the model assumes 0 capacitance, resistance, inductance, and voltage in the test load.
ibis models 10-3 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 10.3 i/o model application note the AMD-640 system controller i/o buffer ibis models and their applications can be found in the AMD-640 system controller i/o model (ibis) application note , order# (tbd). the model is available at http://www.amd.com 10.4 i/o buffer ac and dc characteristics refer to section 9 for the AMD-640 system controller ac timing specifications. refer to section 8 for the AMD-640 system controller dc specifications. 10.5 references ease system simulation with ibis device models by syed huq, electronics design , december 2, 1996 ibis 2.1 specification at http://vhdl.org/ ibis forum i/o buffer modeling cook book
10-4 ibis models AMD-640 system controller data sheet 21090c/0june 1997 preliminary information
pin descriptions 11-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 11 pin descriptions 11.1 electrical considerations reset during reset, bidirectional pins are tri-stated, and outputs are driven to their inactive state. configuration certain pci pins require pullup resistors (recommended value 8.2 kohms). their names and pin numbers are as follows: ? devsel# k-2 ? frame# l-3 ? irdy# k-1 ? lock# k-3 ? par# j-3 ? req0# c-2 ? req1# e-5 ? req2# a-1 ? req3# c-1 ? serr# j-1 ? stop# h-5 ? trdy# k-4 11.2 pin numbering the following tables list the AMD-640 system controller pin names and their corresponding pin numbers. table 11-1 groups the pins by function. table 11-2 presents the pins as they appear on the 328-pin ball grid array.
11-2 pin descriptions AMD-640 system controller data sheet 21090c/0june 1997 preliminary information table 11-1. functional grouping host address host data host control pci addr/data pci control cache interface pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name. pin no. pin name pin no. ha3 ha4 ha5 ha6 ha7 ha8 ha9 ha10 ha11 ha12 ha13 ha14 ha15 ha16 ha17 ha18 ha19 ha20 ha21 ha22 ha23 ha24 ha25 ha26 ha27 ha28 ha29 ha30 ha31 v-11 y-11 u-8 y-12 y-8 v-8 v-7 y-7 w-7 u-7 y-6 v-6 w-6 u-6 y-5 w-5 v-5 u-5 v-9 u-10 u-p w-10 w-9 v-10 y-9 y-10 u-11 w-11 w-8 hd0 hd1 hd2 hd3 hd4 hd5 hd6 hd7 hd8 hd9 hd10 hd11 hd12 hd13 hd14 hd15 hd16 hd17 hd18 hd19 hd20 hd21 hd22 hd23 hd24 hd25 hd26 hd27 hd28 hd29 hd30 hd31 hd32 hd33 hd34 hd35 hd36 hd37 hd38 hd39 hd40 hd41 hd42 hd43 hd44 hd45 hd46 hd47 hd48 hd49 hd50 hd51 hd52 hd53 hd54 hd55 hd56 hd57 hd58 hd59 hd60 hd61 hd62 hd63 y-1 y-3 y-2 y-4 w-1 w-2 v-1 r-1 u-1 w-3 v-3 w-4 t-1 v-4 u-3 v-2 u-4 t-3 u-2 r-3 t-4 r-2 t-2 p-1 r-4 p-3 p-2 n-1 p-4 n-3 n-2 n-4 m-3 m-2 k-1 m-4 j-2 j-1 j-4 h-1 h-2 g-2 j-3 g-4 h-4 g-1 h-3 f-2 f-1 g-3 f-4 f-3 e-1 e-4 e-2 d-1 e-3 d-3 d-2 c1 c-2 c-3 b-1 a-1 ads# ahold be0# be1# be2# be3# be4# be5# be6# be7# boff# brdy# cache# d/c# eads# hitm# hclk hlock# ken#/inv m/io# na# reset# smiact# w/r# t-5 l-5 k-2 k-3 k-4 l-1 l-2 l-3 l-4 m-1 p-5 m-5 j-5 t-7 r-5 t-8 k-16 g-5 k-5 h-5 n-5 t-15 t-10 t-9 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 a-15 a-14 b-13 a-13 c-12 b-12 a-12 c-11 a-11 c-10 b-10 a-10 c-9 b-9 a-9 c-8 c-7 b-7 a-7 c-6 b-6 a-6 c-5 b-5 d-6 c-4 b-4 a-4 b-3 a-3 b-2 a-2 c/be0# c/be1# c/be2# c/be3# devsel# frame# gnt0# gnt1# gnt2# gnt3# irdy# lock# par pclk pgnt# preq# req0# req1# req2# req3# serr# stop# trdy# b-11 a-5 a-8 b-8 e-9 e-6 d-8 d-10 d-12 d-14 e-7 e-5 e-12 e-10 d-5 d-4 d-7 d-9 d-11 d-13 e-13 e-11 e-8 bwe# cads# cadv# ce1# coe# gwe# tagwe# ta9 ta8 ta7 ta6 ta5 ta4 ta3 ta2 ta1 ta0 y17 w15 v15 w16 u15 y16 v16 y19 w19 y18 w18 v18 t14 v17 u17 u16 p16
pin descriptions 11-3 21090c/0june 1997 AMD-640 system controller data sheet preliminary information table 11-1. functional grouping (continued) dram address dram data dram control power power ground pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. ma0 ma1 ma2 ma3 ma4 ma5 ma6 ma7 ma8 ma9 ma10 ma11 ma12 ma13 v-12 t-12 y-13 w-13 v-13 u-13 t-13 w-14 u-14 y-15 y-14 v-14 f-7 n-16 md0 md1 md2 md3 md4 md5 md6 md7 md8 md9 md10 md11 md12 md13 md14 md15 md16 md17 md18 md19 md20 md21 md22 md23 md24 md25 md26 md27 md28 md29 md30 md31 md32 md33 md34 md35 md36 md37 md38 md39 md40 md41 md42 md43 md44 md45 md46 md47 md48 md49 md50 md51 md52 md53 md54 md55 md56 md57 md58 md59 md60 md61 md62 md63 w-20 t-17 t-19 r-20 p-19 n-18 l-20 k-19 f-18 d-20 c-19 c-18 b-18 b-16 b-15 c-13 u-18 u-20 r-18 p-17 n-20 m-19 l-18 j-20 e-19 e-17 d-18 a-19 c-17 a-17 d-16 b-14 v-19 u-19 t-20 r-17 p-18 m-20 l-19 k-18 f-19 e-18 c-20 a-20 d-17 c-16 d-15 c-14 v-20 t-18 r-19 p-20 n-19 m-18 k-20 j-19 e-20 d-19 b-20 b-19 a-18 b-17 a-16 c-15 cas7# cas6# cas5# cas4# cas3# cas2# cas1# cas0# ras5# ras4# ras3# ras2# ras1# ras0# scasa# scasb# scasc# srasa# srasb# srasc# wea# web# wec# mpd7 mpd6 mpd5 mpd4 mpd3 mpd2 mpd1 mpd0 l16 g16 j16 h16 l17 h17 k17 j17 n17 m17 e16 f16 f17 g17 w12 u12 p6 y20 w17 h6 m16 g15 t11 g18 h20 g20 h18 f20 j18 g19 h19 v dd e14 g6 v dd3 f5 f6 f14 f15 p15 r6 r7 r15 r16 ground e15 j9 j10 j11 j12 k9 k10 k11 k12 l9 l10 l11 l12 m9 m10 m11 m12 t6 t16
11-4 pin descriptions AMD-640 system controller data sheet 21090c/0june 1997 preliminary information table 11-2. AMD-640 system controller pin diagram (top view) key1234567891011121314151617181920 a hd63 ad31 ad29 ad27 cbe3 ad21 ad18 cbe2# ad14 ad11 ad8 ad6 ad3 ad1 ad0 md62 md29 md60 md27 md43 b hd62 ad30 ad28 ad26 ad23 ad20 ad17 cbe1# ad13 ad10 cbe0# ad5 ad2 md31 md14 md13 md61 md12 md59 md58 c hd59 hd60 hd61 ad25 ad22 ad19 ad16 ad15 ad12 ad9 ad7 ad4 md15 md47 md63 md45 md28 md11 md10 md42 d hd55 hd58 hd57 preq# pgnt# ad24 req0# gnt0# req1# gnt1# req2# gnt2# req3# gnt3# md46 md30 md44 md26 md57 md9 e hd52 hd54 hd56 hd53 lock# frame# irdy# trdy# devsel# pclk stop# par serr# vdd5 gnd ras3# md25 md41 md24 md56 f hd48 hd47 hd51 hd50 vdd3 vdd3 ma12 vdd3 vdd3 ras2# ras1# md8 md40 mpd3 g hd45 hd41 hd49 hd43 hlock# vdd5 web# cas6# ras0# mpd7 mpd1 mpd5 h hd39 hd40 hd46 hd44 m/io# srasc# cas4# cas2# mpd4 mpd0 mpd6 j hd37 hd36 hd42 hd38 cache# gnd gnd gnd gnd cas5# cas0# mpd2 md55 md23 k hd34 be0# be1# be2# ken# gnd gnd gnd gnd hclk cas1# md39 md7 md54 l be3# be4# be5# be6# ahold gnd gnd gnd gnd cas7# cas3# md22 md38 md6 m be7 hd33 hd32 hd35 brdy# gnd gnd gnd gnd wea# ras4# md53 md21 md37 n hd27 hd30 hd29 hd31 na# ma13 ras5# md5 md52 md20 p hd23 hd26 hd25 hd28 boff# scasc# vdd3 ta0 md19 md36 md4 md51 r hd7 hd21 hd19 hd24 eads vdd3 vdd3 vdd3 vdd3 md35 md18 md50 md3 t hd12 hd22 hd17 hd20 ads# gnd d/c# hitm# w/r# smiact# swec# ma1 ma6 ta4 reset# gnd md1 md49 md2 md34 u hd8 hd18 hd14 hd16 ha20 ha16 ha12 ha5 ha23 ha22 ha29 scasb# ma5 ma8 coe# ta1 ta2 md16 nmd33 md17 v hd6 hd15 hd10 hd13 ha19 ha14 ha9 ha8 ha21 ha26 ha3 ma0 ma4 ma11 cadv# tagwe# ta3 ta5 md32 md48 w hd4 hd5 hd9 hd11 ha18 ha15 ha11 ha31 ha25 ha24 ha30 scasa# ma3 ma7 cads# ce1# srasb# ta6 ta8 md0 y hd0 hd2 hd1 hd3 ha17 ha13 ha10 ha7 ha27 ha28 ha4 ha6 ma2 ma10 ma9 gwe# bwe# ta7 ta9 srasa#
package specifications 12-1 21090c/0june 1997 AMD-640 system controller data sheet preliminary information 12 package specifications the AMD-640 system controller comes in a 328-pin plastic ball grid array (pbga). the dimensions and thermal specification are shown below. q ja <= 25 o c/w q jc = not available. replaced by y j-t, also not available. table 12-1. 328-pin bga package preliminary specification symbol millimeters inches notes min max min max a 26.80 27.20 1.055 1.071 b 24.03 24.23 0.946 0.954 c 24 24 0.945 0.945 ref d 24 24 0.945 0.945 ref e 2.20 2.46 0.087 0.097 f 1.17 1.17 0.046 0.046 ref g 0.56 0.56 0.022 0.022 ref h 0.50 0.70 0.020 0.028 m 1.27 1.27 0.050 0.050 nom
12-2 package specifications AMD-640 system controller data sheet 21090c/0june 1997 preliminary information figure 12-1. 328-pin bga package preliminary specification a a b b c d e f m h h 0.150 t g a b c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d e f g h j k l m n p r t u v w y

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